Hi,
As my design intent was supposed to act as a dual-port ram and by default, I have kept my reset value to 'h12 to all memory locations once it goes low(active low reset), but why is my monitor unable to capture the value ('h12) after apply_reset() is initiated in my test class for first 5 clock edges. Is it my RTL design error or something else, I can’t really figure it out.
Please let me know if there is any logical error or something. Please check the scoreboard for the same
The link for EDA is DPRAM
Thank You
In reply to sai_pra99:
You should never have parallel always@() blocks write the same data elements.
In your memory, you should have just one always @() block that handles both ports. Also, what is the expected behavior if the both ports write to the same address?
In reply to cgales:
In reply to sai_pra99:
You should never have parallel always@() blocks write the same data elements.
In your memory, you should have just one always @() block that handles both ports. Also, what is the expected behavior if the both ports write to the same address?
Ok, for the latter part I have added a constraint saying {addrA!=addrB ;}, I guess this won’t make two different ports write/read on the same address. And as you told I have kept the portB signals too in one always block. But still, I am facing the same issue.
DPRAM
In reply to sai_pra99:
You are declaring your ram array incorrectly. The number of array elements is not correct.
In reply to cgales:
Thank You, I resolved it
DPRAM
In reply to sai_pra99:
There is a direct relationship between the address width and memory depth. You should use this relationship instead of specifying two separate parameters to eliminate the possibility of design errors due to mismatches.