As my design intent was supposed to act as a dual-port ram and by default, I have kept my reset value to 'h12 to all memory locations once it goes low(active low reset), but why is my monitor unable to capture the value ('h12) after apply_reset() is initiated in my test class for first 5 clock edges. Is it my RTL design error or something else, I can't really figure it out.
Please let me know if there is any logical error or something. Please check the scoreboard for the same
The link for EDA is DPRAM