Lack of useful information about UVM

Hi,
I have read lot of manuals about UVM here and I didn’t find clear information about using it for writing real-life verification designs. There is mostly information about UVM’s classes and very simple artificial examples without explaining how to properly couple TLM, RTL and testbench without race conditions and non-determenism. Simple example of TLM2.0 nonblocking transport in the UVM library archive apparently contains inconsistency with TLM2.0 standard. I am confused to use UVM because I have no idea how to properly use it.

Albert

In reply to Fitc:

I have seen that run_test(); function is called in module block at some examples that can lead to race conditions between RTL and testbench. As far as I know it must be called in program block to be executed in reactive regions of time slot.

Albert

It might help to explain what goal you are trying to achieve that had you interested in looking at the UVM. Every verification environment is different and the purpose of the Verification Cookbook is to explain basic concepts common to all.

You may want to see the following references

The missing link: The DUT to Testbench Connection

Are Program Blocks Necessary?

In reply to dave_59:

Dave,
Thank you! It’s very interesting.

Albert