Is it possible to drive value to clocking block input signal from top module?

Hi,

I’m new to UVM. is it possible assign 1 to input of clocking req signal in top module.
please find code in below.

interface intf ();
logic req;
logic grand;

clocking cb @(posedge clk);
    input req;
    output grand; 
endclocking : cb

modport md(
    clocking cb,
    input req,
    output grand);
top module
intf vif();
assign vif.md.cb.req = 1;
endmodule

Kindly help me.

In reply to amsaveni.c:

This is more of a SystemVerilog question rather than UVM.

You can only make procedural “drive” assignments to clocking block outputs, and they will get updated relative the the clocking event.

If you had written

top module
 intf vif();
 initial  vif.cb.grand <= 1;
endmodule

That assignment would update at the first posedge of clk.
You can always assign to the direct signals in an interface, regardless of whether or not you are using a clocking block. So you could have written

top module
 intf vif();
 initial  vif.req = 1;
//or 
 assign vif.req = 1;
endmodule

You can also use variable declaration initializations.
Note that there is no referencing the modport md here. Modports are only used in port connections or in virtual interface declarations.

interface intf ();
  logic req = 1;
  logic grand = 0;
  bit clk;
 
  clocking cb @(posedge clk);
    input req;
    output grand; 
  endclocking : cb
 
  modport md(
    clocking cb,
     ); // do not put other signals in if you are using a clocking block
endiniterface