Is it possible to add a verilog model inside an agent?

I have an agent that will be duplicated multiple times in the testbench. However I want to use a separate Verilog model to change the protocol data coming in to another type of protocol data. Where would I put this instantiation? I’ve tried putting it inside one of the phases but I get compile errors, and I’ve also tried putting the instantiation right after the class declaration during the variable declaration section and still get errors.

In reply to camilo.montenegro:

What do you mean with different protocol? And what does it mean you wan to use a specific agent multiple times?
If you want to drive a different interface/protocol from a driver the you have more than 1 agent.

In reply to camilo.montenegro:

Can you clarify what you mean by “model” is this a class instance? If so, do understand the UVM class factory for this purpose?