So,first I am learning uvm. The partitioning of what should be checked at transaction level or signal level is not always obvious to me.
I have seen monitor instantiating handle to register model.By monitor I mean the component transforming signal into transaction sent to the scoreboard.
Is it correct if this component used information from register bank ?
For example, we can consider the case of UVC of serial interface slave. To check if the slave should reply or not to the master request, it is needed to know the value of the register slave id/address.
1)if the monitor has access to the register value, the monitor can do the check. if the serial interface support arbitration process, the monitor can also check the bus arbitration process.
2)if the monitor does not have access to this register value, it should report more info in the transaction,so the scoreboard can check if the slave should reply or not.
The monitor should also sent all information needed to check bus arbitration.
What is the correct method ?