Issue in setting up Hdl path in RAL

UVM
, ,
1

Hi,
Need help.
I am facing an issue in setting up hdl path.

Using back door access,
this is the access hdl path: top.dut_i.x_i.y_i.z_i.reg
Here top - Top Module
dut_i - dut Module instance name
x_i - x Module instantiated in dut module
y_i - y Module instantiated in x module
z_i - z Module instantiated inside a

generate

block in y module

when I ran the simulation I am getting this error:

" UVM_ERROR: set: unable to locate hdl path (top.dut_i.x_i.y_i.z_i.reg)

Either the name is incorrect, or you may not have PLI/ACC visibility to that name "

But in other way I have tried to access these below paths all are working fine

  1. hdl access path: top.dut_i.x_i.y_i.reg_x
  2. hdl access path: top.dut_i.x_i.reg_y
  3. hdl access path: top.dut_i.reg_z

I think the problem is with the RAL in accessing instance path through

generate

block.

How to resolve this?

Thanks in advance
Rajashekhar

2

If your ‘z’ module is instantiated within a generate inside the ‘y’ module, this generate will create another level of hierarchy. Have a look in the hierarchy browser in your tool’s GUI to see exactly how this looks like. Most likely it’s going to be something like:

dut_i.x_i.y_i.block0.reg

where the ‘block0’ part is going to depend on your simulator (different simulators call unnamed blocks differently).

3

In reply to Tudor Timi:

Thanks for the answer.

I have checked the hierarchy and made changes its working now.

I am using Questasim its hierarchy is dut_i.x_i.genblk.y_i.reg