Hi All,
I am facing a issue, where when I am writing to a register, the coverage bin for write is getting hit for initialized value, but not for the actual value written. To explain more:
My register class looks like this:
class er_pcie_line_rate_i14_t extends uvm_reg;
rand uvm_reg_field pad26; //
rand uvm_reg_field value; //
virtual function void build();
pad26 = uvm_reg_field::type_id::create("pad26");
pad26.configure(this, 26, 6, "RW", 1, `UVM_REG_DATA_WIDTH'h0000000, 1, 1, 0); // Default value is "n/a", set to 0 and disable.
value = uvm_reg_field::type_id::create("value");
value.configure(this, 6, 0, "RW", 0, `UVM_REG_DATA_WIDTH'h00, 1, 1, 1);
wr_cg.set_inst_name($sformatf("%s.wcov", get_full_name()));
rd_cg.set_inst_name($sformatf("%s.rcov", get_full_name()));
endfunction
covergroup wr_cg; // Fields with default value = "n/a" is removed from cover group.
option.per_instance=1;
value : coverpoint value.value[5:0] {
option.auto_bin_max = 4; // Cover group restricted to 4 bins
}
endgroup
covergroup rd_cg; // Fields with default value = "n/a" is removed from cover group.
option.per_instance=1;
value : coverpoint value.value[5:0] {
option.auto_bin_max = 4; // Cover group restricted to 4 bins
}
endgroup
protected virtual function void sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map);
super.sample(data, byte_en, is_read, map);
if(!is_read) wr_cg.sample();
if(is_read) rd_cg.sample();
endfunction
`uvm_register_cb(er_pcie_line_rate_i14_t, uvm_reg_cbs)
`uvm_set_super_type(er_pcie_line_rate_i14_t, uvm_reg)
`uvm_object_utils(er_pci_line_rate_i14_t)
function new(input string name="er_pci_line_rate_i14_t");
super.new(name, 32, build_coverage(UVM_CVR_FIELD_VALS));
wr_cg=new;
rd_cg=new;
endfunction
endclass : er_pcie_line_rate_i14_t
The number of bins getting created are 4 and bins are as follows:
auto[0:15]
auto[16:31]
auto[32:47]
auto[48:63]
The initial value of register is 0 for which the WRITE bin auto[0:15] is getting hit, but around 15000ns, I am writing to this register with value 1B for which the WRITE bin auto[16:31] is not getting hit.
The register model is automatically generated and I believe, whenever WRITE will happen, the bin should get hit, which is not happening in my case.
I tried register.sample_value() after register write, but WRITE bin is still un-hit.
Please suggest me, what can be done?