iam using the UVM register sequences to test my reg block. one of the seq "uvm_reg_access_seq" which does front door write followed by backdoor read to the reg block and vice versa. I see an issue and the backdoor reads are failing. i tried to debug it further goes deep into the DPI calls and iam unable to proceed
My seq call:
reg_access_seq = uvm_reg_access_seq_temp::type_id::create("reg_access_seq");
UVM_ERROR /share/edasw/cadence/XCELIUM/20.12.001/tools/methodology/UVM/CDNS-1.2/sv/src/reg/uvm_reg.svh(2899) @ 121276000: reporter [RegModel] Register "regblock.axi.eth_status_fields" value read from DUT (0x00000000000101ff) does not match mirrored value (0x00000000000000ff)
the bits 8 and 16 are R/W bits with set to 1 on reset.
Any pointers are appreciated.