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  • Issue in read registers via RAL model - return always 0

Issue in read registers via RAL model - return always 0

UVM 6659
issue#RAL#read#0 1
Shira_S
Shira_S
Full Access
2 posts
January 08, 2023 at 12:50 am

I created RAL model in my UVM env. Write via RAL is working fine, I see that the requested value is writting well in the relevant register.
My issue is in read register. Read via RAL model is returning always 0 whereas my monitor is reading the good value.
In RAL model, I have a predictor that is connected to TLM monitor, and all seems to be connected well. (adapter...)
My create_map in my register model is such:

reg_block_map = create_map("reg_block_map", 'h0, 2, UVM_NO_ENDIAN, 1);
(my registers are at size 16 bits)

Where am I wrong? What is the cause of my issue?

Thanks!

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cgales
cgales
Forum Moderator
1951 posts
January 09, 2023 at 7:40 am

In reply to Shira_S:

You should verify that your register adapter functions (reg2bus and bus2reg) are functioning correctly. If you aren't seeing the correct values when performing reads, it's possible that the bus2reg function isn't putting the read data from the bus into the register properly.

Solution

Solution

Shira_S
Shira_S
Full Access
2 posts
January 09, 2023 at 9:46 am

In reply to cgales:

I resolved my issue. I missed to update req.data with the read_data value in my driver before sending the request.
Since the register model is receiving transaction from monitor but also from driver, the read_data should be updated also in driver request.

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