Hello all, I hope you’re doing well.
I’m facing some issues and i’m lost after debugging .
I’m working with a 2stage pipelined bus protocol (Addr phase and data phase). In monitor, I did as follows
// run phase
fork
rand_delay_pro // this a process where i drive some signals of the interface to low/high for a random clk cycle
mtr_item_process;
join
// mtr_item_process;
task mtr_item_process;
wait(reset_n) // wait for reset diabling in case it was enabled
if (// some conditions on interface sign to caputre data phase) begin
// collect data phase values
complete_txn.write(item_rw) // complete txns ( addr and data ) to write it to scoreboard
`uvm_info("SCB :",$sformat(" item to scoreboard addr :%x, data :%",item_rw.addr,item_rw.data),UVM_LOW);
end
if((// some conditions on interface sign to caputre addr phase) begin
// collect addr phase values
end
else @(posedge of clk)
endtask
In scoreboard, i use get txn from monitor through analyisi port that i connected to a fifo
// run phase
sc_ap_fifo.get( item_rw);
`uvm_info("SCB :",$sformat(" item from monitor addr :%x, data :%",item_rw.addr,item_rw.data),UVM_LOW);
The problem appears when I run the test and i get the uvm_info ( of monitor and scoreboard), the data didn’t change hwoever the addr changed ( I think because of piplining of the bus cuz the addr comes first), i coded the 2 messages of uvm_info at the same cycle how ever addr changed
What u think of this problem ? have anyone faved that before ? How can I fix this?
Thanks in advance