Issue data on posedge or negedge?

UVM
1

Hi All,

I want to create a new interface UVC for verification requirements.
I wondering when the driver needs to issue the data to DUT ,on posedge clock or negedge clock.
The design moduls transfer data on posedge clock.

As I understand the interface UVC should behave as the design moduls which means to drive the data on posedge clock
Am i right?
what is the advantage of issung data on negedge and not on posedge

Thanks
Maor

2

In reply to maor:

As you understand, a testbench UVC is just an alternative model for a part of a design that is not being tested, so you can drive your testbench just as the design does on the posedge clock (using non-blocking assignments of course). But since the testbench is not being synthesized you do have a number of alternatives, including the negedge, clocking blocks, plus a few other way of skewing the stimulus that I would not advise.

Two places I can think of where it might be more advantageous to use the negedge are

  • Viewing waveforms. For some people, it might be easier to see which signals are driven by the testbench, and which are driven by the DUT. For other people it might confuse them further.
  • Gate-level simulation might require skewing the stimulus for timing and correct clock synchronization.

In any case, you might not be able to simply use the negedge clock if there are multiple clocks or clock gating.