Invalid Register access

UVM
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1

I have generated register model (range 0x0 to address 0x60), I want perform a read/write to an address location that is out-of-bounds like 0x70.
what are the ways to access or perform read/write on that invalid reg addr?

2

Hi araj380,

If we want to write an illegal address which is not there in the Register model. It will not be possible and will throw an error. Because the register definition itself has to present in the register model. If you want to write an illegal address, you can simply follow usual process.

Or else define a junk register in the register file with an offset of 0x70 and the checking of valid address logic has to present in the monitor and has to give a warning saying invalid register access. Then you can write to that address using RAL model to DUT. DUT wont give any data wrt that register, and we will get error response from the Design. You can then compare the Test bench write/read with DUT response which should be always ended up with error only because of invalid address.

Thanks,
Furry_Panda

3

In reply to Furry_Panda:

I need that error
I have created one dummy register and tried reading out of bound offset…But design response is normal …nothing unsuual

4

In reply to sunking:

It’s a benefit to use register names instead of register addresses, because these addresses might change several times during the development process.
Reading from an illegal address is the same than reading from a register name which does not exist. This should be reported.

5

In reply to sunking:

In reply to Furry_Panda:
I need that error
I have created one dummy register and tried reading out of bound offset…But design response is normal …nothing unsuual

I assume ‘created one dummy register’ means you have added dummy register in register model, and this register is not present in RTL. Still if you are not getting error response from design then check whether your design supports error for out of bound access or not. This type of error reporting is design specific feature. May be not implemented/intended or you caught some RTL bug :)