Interrupt handling

UVM
1

Hi,

I have the following question from the post Stimulus/Interrupts | Verification Academy.

In the code below,



 // Read from the GPO register to determine the cause of the interrupt
 assert (req.randomize() with {addr == 32'h0100_0000; read_not_write == 1;});
 start_item(req);
 finish_item(req);

We randomize the req (which is a isr seq item in this case) with the address of ISR, read set.

Can anyone explain, how does this sequence, gets the read_data from the DUT registers. What happens under-the-hood?

Also, in the code below,



 req.read_not_write = 0;
 if(req.read_data[0] == 1) begin
  `uvm_info("ISR:BODY", "IRQ0 detected", UVM_LOW)
  req.write_data[0] = 0;
  start_item(req);
  finish_item(req);
  `uvm_info("ISR:BODY", "IRQ0 cleared", UVM_LOW)
 end

As the item is not randomized, I believe we are writing into address “32’h0100_0000” to clear the interrupt. Is this correct?

Thanks,
Madhu

2

In reply to mseyunni:

Hi Madhu,

To answer your first question:

“Can anyone explain, how does this sequence, gets the read_data from the DUT registers. What happens under-the-hood?”

Take a look at the driver code, it drives the address on to the bus and if it’s a read, copies the data from bus to the request and calls item_done.

Your understanding of second point is correct, the register is written to clear the interrupt.

Thanks,
Rohit