Interface in uvm_test

UVM
,
1

Hi
I am new to UVM. I actually work on a uvm test and I have to write an interface that will link some DUT signals with my test. But I didn’t find examples for this case, only example with driver and monitor. I obtained the same error, my interface is not set. Following my code:

interface int_if(input clk);
logic my signal;
endinterface

class int_if_hand_c;
virtual int_if vif;
endclass

class my_test extends uvm_test;
int_if_hand_c int_if_hand;
virtual int_if vif;

// Constructor:

function build_phase(uvm_phase);

int unsigned success;

        success = uvm_config_db #(virtual int_if)::get(this, "", "vif", vif);
        if (!success) begin `uvm_fatal("CFG","Virtual interface is not set"); end

        success = uvm_config_db #(int_if_hand_c)::get(this, "int_if_hand", "", int_if_hand);
        if (!success) begin `uvm_fatal("CFG","int_if_hand is not set"); end

        uvm_config_db #(virtual interface int_if)::set(this, "", "" ,int_if_hand.vif);

endfunction

endclass

What did I do wrong? Thanks
Juliette

2

Hi Julette,

There are two points to get the interface in the test case:

  1. The interface must be set in the general way in the tb_top in UVM, so over there set the interface as uvm_config_db #(virtual int_if):: set (uvm_root::get, “*”, “intf_hand”, int_if_hand); , this statement does you to get the interface to both higher and lower components in the VE.

  2. Now you can use it directly using get success = uvm_config_db #(virtual int_if)::get(this, “”, “intf_hand”, int_if_hand);

  3. My concern why do you want to set the interface again in the test case build_phase,
    I think so that you have already got the interface and could use the same to
    drive any signals on to the interface.

  4. uvm_config_db #(virtual interface int_if)::set(this, “”, “” ,int_if_hand.vif); syntax is wrong it should be #(virtual int_if) and set has the following arguments set(context,“instance_path”,“string_name”,variable_name).

Thanks,
Nikhil

3

In reply to nchakravarthy:

Thanks a lot for your answer.
So I have some questions: I have to set my interface in the tb_top necessarily? I can’t do this in my test? That what I tried to do in fact…
And Where I should configure the clock and the signals from the DUT of my interface?

Thanks
Juliette

4

In reply to juliette_29:

In UVM we set the physical interface in the tb_top and we get it in the VE, so where ever you get the interface it points to the physical interface.

you can drive the clock period in any component where you get the interface, there is no need to set the interface again as the virtual interface in your test case, it points to the physical interface. Generally we drive the DUT signals in the driver and the clock configuration can be done in test case or you can drive clock in your tb_top.

Thsnks,
Nikhil

5

Thanks a lot for your answer!

6

In reply to nchakravarthy:

Hi Julette,
There are two points to get the interface in the test case:

  1. The interface must be set in the general way in the tb_top in UVM, so over there set the interface as uvm_config_db #(virtual int_if):: set (uvm_root::get, “*”, “intf_hand”, int_if_hand); , this statement does you to get the interface to both higher and lower components in the VE.
  2. Now you can use it directly using get success = uvm_config_db #(virtual int_if)::get(this, “”, “intf_hand”, int_if_hand);
  3. My concern why do you want to set the interface again in the test case build_phase,
    I think so that you have already got the interface and could use the same to
    drive any signals on to the interface.
  4. uvm_config_db #(virtual interface int_if)::set(this, “”, “” ,int_if_hand.vif); syntax is wrong it should be #(virtual int_if) and set has the following arguments set(context,“instance_path”,“string_name”,variable_name).
    Thanks,
    Nikhil

what about test cases extended from base test
i done as below but getting error

ex class test_case2 extends base_test;
virtual lbus_if lbus_vif;
//function new
//start of simulation phase
//build phase
$assertoff(lbus_if.cssss);

endclass: test_case2

7

In reply to DV intern:

It would really help if you posted the error but I’m guessing that $assertoff did not like the virtual interface and wanted to see an actual interface.

8

In reply to dave_59:

Hey Dave, I encounter the above scenario by using disable iff in assertion(in interface file) so that i can control in test cases by interface handle.

but i want to know why it not like Virtual interface ?

in my base test it’s virtual interface, i used that in test cases as $assertoff(lbus_if.cssss);
please suggest how to use vif in $asserton/off
Error: Fatal error (bad handle reference)

9

In reply to DV intern:

The first argument to $assertoff is a numeric level, and the second argument is a scope. A virtual interface variable is not a scope.

I suggest you create a function inside your interface that you can call via a virtual interface handle.

interface bus;

cssss: assert property(....);

function void cssss_off;
   $assertoff(0,cssss);
endfunction

endinterface
10

In reply to dave_59:
Thank you, dave

11

In reply to dave_59:

Hi Dave I have one more doubt, any another way to use the class handle inside the interface?

For example
class config;
bit [9:0] q_value;
endclass

interface

task cal;
if(--------)// I NEED TO USE THE CONFIG Q_VALUE INSIDE THE IF STATEMENT
endtask

endinterface

Is there any way to access the value inside the interface?

12

In reply to DV intern:

Where is the class object being constructed? You can use the uvm_config_db to set and get the handle.