Interface related

UVM
1

Dear seniors,
if any design performing the operations at different clock_frequencies like one write_operation peforming at w_clock,read1_operation performing at r_clock1,read2_operation performing at r_clock2 respectively.

can i write multiple interfaces which
are working at different frequencies (like :- interface in1(input bit w_clock),
interface in2(input bit r_clock1),
interface in3(input bit r_clock2),
)
in side testbench.

Thanks in advance

2

In reply to hurmath@fldec:

Your question is not very clear.

You dont have to define multiple interfaces if only the clock frequency changes. you can just have multiple instances of the same interface each one supplied with different clock. But this really is case specific. If skews in the clocking block are different you might want to have separate interface definitions as well.

3

can I do like that:-

interface in(input bit wr_clock,rd1_clock,rd2_clock);

clocking wdr_cb @(posedge wr_clock);
default input #1 output #1;
// Some inputs and outputs

endclocking

clocking rdr1_cb @(posedge rdr1_clock);
default input #1 output #1;
// Some inputs and outputs

endclocking

clocking rdr2_cb @(posedge rdr2_clock);
default input #1 output #1;

// Some inputs and outputs
endclocking

4

In reply to hurmath@fldec:

hurmath@fldec,

Please follow the guidelines of putting your code into code blocks .

interface in(input bit wr_clock,rd1_clock,rd2_clock);


clocking wdr_cb @(posedge wr_clock);
default input #1 output #1;
// Some inputs and outputs

endclocking

clocking rdr1_cb @(posedge rdr1_clock);
default input #1 output #1;
// Some inputs and outputs

endclocking

clocking rdr2_cb @(posedge rdr2_clock);
default input #1 output #1;

// Some inputs and outputs
endclocking

This should work for your case unless you have same input and outputs in more than one clocking block.

~Pranoy

5

In reply to Pranoy:

Signal might belong to different clocking blocks.

6

char_Sue sir,

my approch is corect or we need to change something.