Interface syntax error

UVM
,
1

hi,

can anyone help me, i am getting these error, i am running on ncsim

ncvlog: *E,ILFSTI (…/rtl//dff_if.sv,1|8): an interface can only be declared at the compilation unit top level, or within an interface [SystemVerilog].
(include file: ../rtl//dff_if.sv line 1, file: ../test/dff_pkg.sv line 8) interface dff_if(input bit clk); | ncvlog: *E,SVNIMP (../rtl//dff_if.sv,1|8): SystemVerilog construct not yet implemented: nested interface. (include file: …/rtl//dff_if.sv line 1, file: …/test/dff_pkg.sv line 8)

2

In reply to LOHIHTHA DM:

hi sir this is my code

`include "/mnt/sandbox1/lohitha_dm/SNIPPET_VERIFICATION/UVM_VERIFICATION/DFF/rtl/dff_if.sv"
module top();
        import uvm_pkg::*;
        import dff_pkg::*;

bit clk=1;
always #10 clk=~clk;

dff_if BUS(clk);
dff DUT(.clk(clk),
        .rst(BUS.rst),
        .d(BUS.d),
        .q(BUS.q),
        .qb(BUS.qb));


initial
begin
        uvm_config_db #(virtual dff_if) :: set (null,"*","vif1_0",BUS);
end
endmodule

and this is my package
package dff_pkg;
import uvm_pkg::*;

`include "uvm_macros.svh"

`include "dff_if.sv"
`include "write_xtn.sv"
`include "wr_config.sv"
`include "rd_config.sv"
`include "env_config.sv"
`include "wr_driver.sv"
`include "wr_monitor.sv"
`include "wr_sequencer.sv"
`include "wr_agt.sv"
`include "wr_agt_top.sv"
`include "wr_seqs.sv"
`include "read_xtn.sv"
`include "rd_monitor.sv"
`include "rd_sequencer.sv"
`include "rd_seqs.sv"
`include "rd_driver.sv"
`include "rd_agt.sv"
`include "rd_agt_top.sv"

`include "virtual_sequencer.sv"
`include "virtual_sequence.sv"
`include "scoreboard.sv"

`include "dff_tb.sv"

`include "test.sv"

endpackage
3

In reply to LOHIHTHA DM:

This line in your package definition is wrong:

`include "dff_if.sv"

Remove it from inside the package.