Interface access for a Subsystem Block

UVM
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1

Hi all,

For the below code, as my Digital Top does not have AHB signals but the 2 subsystem blocks acore and peri_top uses AHB, How do we drive those in our UVM Environment as the interface file shall only contain digital_top signals.
How can I drive the AHB signal in the UVM Environment.

//Digital Top:
module digital_top (
    CLK,
    RST,
    SPI_SCK,
    SPI_MISO,
    SPI_CS,
    SPI_MOSI
);

**ahblite_if #(.ahbAWIDTH(ADDR_AW), .ahbDWIDTH(DATA_DW)) core_mstr_ahb_if();
ahblite_if #(.ahbAWIDTH(ADDR_AW), .ahbDWIDTH(DATA_DW)) peri_mstr_ahb_if();**

//core instantiation
acore acore_top (
//Input signals
.clk(CLKIN),
....
.dbu_ahb_hready         (core_mstr_ahb_if.hreadyout),       // Core AHB master interface               
.dbu_ahb_hresp          (core_mstr_ahb_if.hresp),           
.dbu_ahb_hrdata         (core_mstr_ahb_if.hrdata),             
.dbu_per_ahb_hready     (peri_mstr_ahb_if.hreadyout),       // Peripheral AHB master interface          
.dbu_per_ahb_hresp      (peri_mstr_ahb_if.hresp),             
.dbu_per_ahb_hrdata     (peri_mstr_ahb_if.hrdata),             
....
);
//Peri Top
peri_top u_peri_top (

.CLK              (CLK), 
.RST               (RST),      
.core_mstr_ahb_if   (core_mstr_ahb_if.slave),
.peri_mstr_ahb_if   (peri_mstr_ahb_if.slave)

);

endmodule
2

In reply to ravi.gupta:

Both acore_top and u_peri_top are AHB slave right? In UVM, you can set these interfaces (core_mstr_ahb_if and peri_mstr_ahb_if) to config_db, then get them in uvm_driver component and drive these interfaces depending on the transaction generated from uvm_sequence.

3

In reply to ravi.gupta:

you can instance AHB interface in your testbench top, and directly connect to your sub-module like:

assign dut_top.module_a.htrans = ahb_itf.htrans;
…

and uvm_config_db::set such interface to your driver in env