I would like to know if there is a methodology or existing methodology packages that allow communication from UVM to module.
The reasoning is that testbench lot of randomization decisions are better kept in class/UVM world and use some of these in module world.
For example, I have a clock generator that is highly configurable. I would like to randomize this configuration and use the results to propagate settings from UVM to Verilog clock generator. There are many such use-cases but you get the idea.