I am taking my first go at simming at the top (FPGA chip) level. The first thing I encountered was that our top level contains a Xilinx TEMAC.
I managed to get the required library into my EDA tool, and run the Xilinx provided directed testbench. Great!
I suppose my first job will be developing a BFM that turn transaction into SGMII traffic to provide the TEMAC (by gutting the testbench)…
anyway, my question is…
Is this standard practice to be placing testbench environments around the whole chip, or do engineers try to stay away from simulating “hard IP” at the top level, because it slows the simulation, need to develop a BFM, etc. One option is that I could sim the top level, but apply my stimulus to the other side of the TEMAC (LocalLink) which I already drivers for. Thoughts?