Integrating multiple VIPS with single DUT

UVM
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Hi All,

Please tell me how to integrate multiple VIPS with single DUT.
For eg:
I have DUT which will support I2c and Wishbone…

I have two separate VIPS(I2s and whishbone).
Each VIP is having separate interface

How to integrate two VIPS (having individual interfaces )with single DUT .
Should i need to create single interface & one more top level module having 2 vip instances.

& also please clarify below things.
1)In VIP development we will create Master & slave .bcz Master is working or not ,we will check with slave…viceversa--------Am i correct?

please share any papers or links related to multiple environments.

Thanks,
Nagendra.

2

Hi Nagendra,
The two VIP components you have are simply agents in UVM. Each agent has its own (virtual) interface connection to the DUT, as shown in the UVM Cookbook. Since the virtual interfaces are passed down from the top-level module (make sure you read the follow-on articles: here and here), there is no need to combine your two interfaces into a single interface. Simply pass each interface, the I2s and Wishbone, separately to your testbench through separate uvm_config_db::set() calls.

As to your second question, you should be careful. It’s a good idea, in theory, to have both master and slave VIP components for a given protocol and, yes, you can connect them together to make sure that they work. However, if they are developed by the same person or team, it’s quite possible that they could both have the same error so that they work “correctly” together but actually violate the spec. With pre-packaged VIP, such as Mentor VIP, you can be confident that the protocol is modeled correctly in the VIP, so you just have to worry about getting it right in your DUT.
Good luck,
-Tom

3

Hi All,

My Scenario is single DUT which supports Multiple VIPs from third party. As I am getting VIP environments redily from third party, want to use as it is in SoC testbench. So i want to use multiple environments concept in test class and verify SoC. I am having single DUT which supports multiple protocols like I2C, UART etc with multiple interfaces. I have created instances for multiple interfaces and passed to DUT in top module. Next, I am having doubt with test class like how i instantiate different environments and run the different tests from different VIPs with multiple sequencers and how control over multiple test runs?? Can anyone guide me what would be the best have to do it and what i need to consider??

can anyone guide me docs or links to get idea over my scenario please.

Show some light on my problem please…

4

In reply to babanrosesalluri5:

You don’t run different tests, one for each env. You have different sequences for each sub-env. You are creating virtual sequences describing how the sub-envs should be activated and then you are desfining tests for all your different virtual sequences and starting them in your tests.

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In reply to chr_sue:

Thanks for reply chr_sue. Could you please share some more knowledge about SoC verification and Virtual sequencer concept.

Can you explain me or share documents or links about virtual sequencer in detail. I have some questions and want to get detail idea about below queries. Please help me out

Why we use virtual sequencer ??

what is virtual sequencer and virtual sequence??

how can we control multiple sequences in test bench using virtual sequencer or virtual sequence??
if we can control using two components(virtual sequencer & virtual sequence) can you tell me difference between virtual sequencer and virtual sequence??

what is the difference between virtual sequence/virtual sequencer to non virtual sequence/non virtual sequencer???

When we are writing directed test cases how can we control multiple env/tests in test bench??

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In reply to babanrosesalluri5:

Virtual sequences helps us to synchronize the behavior of multiple agents in our UVM environment.
For details please read
https://verificationacademy.com/cookbook/sequences
and exercise the corresponding code examples.

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In reply to chr_sue:

Thank you chr_sue.

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In reply to tfitz:

With pre-packaged VIP, such as Mentor VIP, you can be confident that the protocol is modeled correctly in the VIP, so you just have to worry about getting it right in your DUT.
Good luck,

I’m stuck at this point.

If my DUT (Device Under Test) only has a bus interface and I am using VIP (Verification IP) for verification, I might wonder if I still need to create a local driver, sequencer, etc.

For example, let’s say my “Timer_DUT” has some registers (reg_A, reg_B, reg_C) and an AHB interface. I can use the AHB VIP, which already has many components implemented, except for the scoreboard. However, AHB VIP is for controlling the AHB bus, not specifically for the Timer_DUT. So, I might think that I need to create UVM components like sequences, sequence items, driver, and monitor for the Timer_DUT.

But since the AHB VIP interfaces with the actual Timer_DUT, some of the components in my Timer_DUT UVM environment might not make much sense, except for the AHB agent.

For instance, the sequencer and driver for the Timer_DUT might not be necessary in my UVM configuration if I simply want to write a value into reg_A on the Timer_DUT and observe what happens.

So, the main question is, if my DUT only consists of bus protocols and is controlled by a VIP, do I still need a my driver or my sequencer, and if yes, how should I configure it? Considering that the AHB driver is already implemented in the VIP, what should I implement in my own driver?