inout port illegal connection error

Question

i have a inout port and i wanna assign it to other varibale at AL and top but it does not work.
Error : inout port illegal connection for port to reg type.

At AL.svh
-----------
inout [31:0] DATA;
--------------

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At top.svh
--------------
AL AL_0(
.DATA(bus_if.DATA)
);
-----------------

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At bus_if.sv
-----------------
logic [31:0] DATA;
-----------------

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i tried to fix much more but it does not work, could you help me? Thanks.

Answer 1

chr_sue

Full Access

3781 posts

June 25, 2019 at 5:40 am

In reply to nrllhclb:

The port declaration
inout [31:0] DATA;

implies this is a nettype (wire). And you want to connect this to a simple variable in your interface. This is not legal.

In your SV interface declare

wire [31:0] DATA,

This'll fix your problem.

Answer 2

nrllhclb

Full Access

8 posts

June 25, 2019 at 5:58 am

In reply to chr_sue:

unfortunately, i tried things which written by you, but it did not.

Answer 3

chr_sue

Full Access

3781 posts

June 25, 2019 at 8:17 am

In reply to nrllhclb:

See here an example:

module des(input logic a, output logic b, inout wire c);
 
endmodule
 
interface intf();
  logic x;
  logic y;
  wire z;
  //logic z;
endinterface
 
module top();
 
intf iface();
des DUT(.a(iface.x), .b(iface.y), .c(iface.z));
endmodule

Replacing the wire in the interface with logic results in the error message:
inout.sv(15): Illegal inout port connection for 'c' (3rd connection).

Answer 4

haykp

Full Access

133 posts

June 30, 2019 at 6:51 pm

In reply to nrllhclb:

Just remember that logic cannot be connect to inout~

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