when I declared “a” as logic it’s working ok but when I declared “a” as wire then tools give me error: This or another usage of “it.a” inconsistent with ‘net’ object.
interface intf(input clk);
wire a;
endinterface
class driver;
virtual interface intf it;
@(it.clk)
it.a <=0;
endclass
In reply to Henriques:
You cannot use procedural assignments directly to drive wires. You can only use continuous assignments or go through a clocking block. Please see Dave’s DVCon paper
https://verificationacademy.com/resources/technical-papers/the-missing-link-the-testbench-to-dut-connection