incompatible class assignment error

Question

hello, forum

I am getting the below error

Error-[SV-ICA] Illegal class assignment
axi_test_top.sv, 79
"this.sq_transaction_w = uvm_object_registry#($unit::eit_axi_master_write_transaction#(32,32),"<unknown>")::create("sq_transaction_w", this, /* contxt = "\000" */);"
  Expression 
  'uvm_object_registry#($unit::eit_axi_master_write_transaction#(32,32),"<unknown>")::create("sq_transaction_w",
  this, )' on rhs is not a class or a compatible class and hence cannot be 
  assigned to a class handle on lhs.
  Please make sure that the lhs and rhs expressions are compatible.
  Instance stack trace:
      test_main#(32,32)  testbench.sv, 19
      testbench  testbench.sv, 5
 
 
 
Error-[SV-ICA] Illegal class assignment
axi_test_top.sv, 80
"this.sq_transaction_r = uvm_object_registry#($unit::eit_axi_master_read_transaction#(32,32),"<unknown>")::create("sq_transaction_r", this, /* contxt = "\000" */);"
  Expression 
  'uvm_object_registry#($unit::eit_axi_master_read_transaction#(32,32),"<unknown>")::create("sq_transaction_r",
  this, )' on rhs is not a class or a compatible class and hence cannot be 
  assigned to a class handle on lhs.
  Please make sure that the lhs and rhs expressions are compatible.
  Instance stack trace:
      test_main#(32,32)  testbench.sv, 19
      testbench  testbench.sv, 5

this is the testbench code

`include "interface.sv"
`include "axi_test_top.sv"
 
//TOP TESTBENCH
module testbench;
 
  bit clk,reset;
 
  parameter ADDR_WIDTH=32;
  parameter DATA_WIDTH=32;  
 
  always #10 clk = ~clk;
 
  initial begin
    reset = 1;
  end
 
  eit_axi_interface #(.ADDR_WIDTH(ADDR_WIDTH),.DATA_WIDTH(DATA_WIDTH)) intf(clk,reset);
  typedef test_main#(ADDR_WIDTH,DATA_WIDTH) test;
 
  initial begin 
    //enable wave dump
    uvm_config_db#(virtual eit_axi_interface#(.ADDR_WIDTH(ADDR_WIDTH),.DATA_WIDTH(DATA_WIDTH)))::set(uvm_root::get(),"*","intf",intf);
    $dumpfile("dump.vcd"); 
    $dumpvars;
  end
 
  //calling test
  initial begin 
    run_test("test_main");
  end
 
endmodule

this is the test code

`define MAX_ADDR 5000
`define READ_ONLY_STARTING_ADD 2000
`include "slave_memory.svh"
`include "slave_memory.sv"
`include "axi_slave_configuration.sv"
//`include "axi_master_configuration.sv"
`include "env_config.sv"
`include "axi_master_transaction.sv"
`include "axi_master_sequence.sv"
`include "axi_environment.sv"
 
//TEST CLASS
class test_main #(int ADDR_WIDTH=32,DATA_WIDTH=32) extends uvm_test;
 
  //------------------------------------------
  //register class to factory by name and by type both
  //------------------------------------------
  typedef uvm_component_registry #(test_main#(ADDR_WIDTH,DATA_WIDTH),"test_main") type_id;
 
  static function type_id get_type();
    return type_id::get();
  endfunction:get_type
 
  virtual function uvm_object_wrapper get_object_type();
    return type_id::get();
  endfunction:get_object_type
 
  const static string type_name=$sformatf("test_main#(%0d,%0d)",ADDR_WIDTH,DATA_WIDTH);
 
  virtual function string get_type_name();
    return type_name;
  endfunction:get_type_name
 
  //environmnt config class instance
  env_config#(ADDR_WIDTH,DATA_WIDTH) e_config;
 
  //slave configuration configuration,class handle
  axi_slave_configuration#(ADDR_WIDTH,DATA_WIDTH)  slv_config;  
 
  //env & sequence instance 
  axi_env #(ADDR_WIDTH,DATA_WIDTH) env_obj;
  master_write_generator_sequence #(ADDR_WIDTH,DATA_WIDTH) seq_w;
  master_read_generator_sequence  #(ADDR_WIDTH,DATA_WIDTH) seq_r;
 
  eit_axi_master_transaction #(ADDR_WIDTH,DATA_WIDTH) sq_transaction;
  eit_axi_master_read_transaction #(ADDR_WIDTH,DATA_WIDTH)  sq_transaction_w;
  eit_axi_master_write_transaction #(ADDR_WIDTH,DATA_WIDTH) sq_transaction_r;
 
  // constructor
  function new(string name = "test_main",uvm_component parent=null);
    super.new(name,parent);  
  endfunction : new
 
  //Build Phase
  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
 
    ...
 
    sq_transaction = eit_axi_master_transaction#(ADDR_WIDTH,DATA_WIDTH)::type_id::create("seq_item",this);
    sq_transaction_w = eit_axi_master_write_transaction#(ADDR_WIDTH,DATA_WIDTH)::type_id::create("sq_transaction_w",this);//ERRORNEOUS LINE(HELP NEEDED HERE)
    sq_transaction_r = eit_axi_master_read_transaction#(ADDR_WIDTH,DATA_WIDTH)::type_id::create("sq_transaction_r",this); //ERRORNEOUS LINE(HELP NEEDED HERE)
 
    ...
 
  endfunction : build_phase
 
  ....
  ....
 
endclass : test_main

this is the sequence file code

class master_write_generator_sequence #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) extends uvm_sequence;
 
   `uvm_object_param_utils(master_write_generator_sequence #(ADDR_WIDTH,DATA_WIDTH))
 
  // uvm_analysis_port #(eit_axi_master_write_transaction #(ADDR_WIDTH,DATA_WIDTH)) gen_scb_write;
 
 
   eit_axi_master_write_transaction #(ADDR_WIDTH,DATA_WIDTH) trans_w,trans_w_scb;
 
  //Constructor
  function new(string name = "master_write_generator_sequence Created");
    super.new(name);
 
  endfunction
 
  virtual task pre_body();
   // gen_scb_write = new("gen_scb_write", this);
  endtask
 
  virtual task body();
 
 // scb sending problem
 
    trans_w = eit_axi_master_write_transaction#(ADDR_WIDTH,DATA_WIDTH)::type_id::create("Processes for genration of eit_axi_master_write_transaction request");
 trans_w_scb = eit_axi_master_write_transaction#(ADDR_WIDTH,DATA_WIDTH)::type_id::create("Processes for genration of eit_axi_master_write_transaction request");
 
/// config class adition...........................
  repeat(2) 
      begin
   `uvm_do (trans_w);
    trans_w_scb.copy(trans_w);
    //gen_scb_write.write(trans_w_scb);
 end
  endtask
 
endclass
 
 
class sequencer_write#(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) extends uvm_sequencer;
 
  `uvm_component_param_utils(sequencer_write #(ADDR_WIDTH,DATA_WIDTH))
 
  //constructor
  function new(string name, uvm_component parent);
    super.new(name,parent);
  endfunction
 
endclass
 
class master_read_generator_sequence #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) extends uvm_sequence;
 
   `uvm_object_param_utils(master_read_generator_sequence #(ADDR_WIDTH,DATA_WIDTH))
 
  // uvm_analysis_port #(eit_axi_master_read_transaction #(ADDR_WIDTH,DATA_WIDTH)) gen_scb_read;
 
    eit_axi_master_read_transaction #(ADDR_WIDTH,DATA_WIDTH) trans_r,trans_r_scb;
 
  //Constructor
  function new(string name = "master_read_generator_sequence Created");
    super.new(name);
  endfunction
 
  virtual task pre_body();
   // gen_scb_read = new("gen_scb", this);
  endtask
 
  virtual task body();
 
 // scb sending problem
    trans_r = eit_axi_master_read_transaction#(ADDR_WIDTH,DATA_WIDTH)::type_id::create("Processes for genration of eit_axi_master_read_transaction request");
trans_r_scb = eit_axi_master_read_transaction#(ADDR_WIDTH,DATA_WIDTH)::type_id::create("Processes for genration of eit_axi_master_read_transaction request");
 
/// config class adition...........................
    repeat(2) 
      begin
   `uvm_do (trans_r);
    trans_r_scb.copy(trans_r);
    //gen_scb_read.write(trans_r_scb);
 
   end
  endtask
 
endclass
 
 
class sequencer_read#(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) extends uvm_sequencer;
 
  `uvm_component_param_utils(sequencer_read #(ADDR_WIDTH,DATA_WIDTH));
 
  //constructor
  function new(string name, uvm_component parent);
    super.new(name,parent);
  endfunction
 
endclass

can anyone help?

Thanks & Regards
jj_bukhari

Answer 1

dave_59

Forum Moderator

9459 posts

September 25, 2020 at 8:15 am

In reply to jj_bukhari:

You need to show use the definition of eit_axi_master_read_transaction.

— Dave Rich, Verification Architect, Siemens EDA

Answer 2

jj_bukhari

Full Access

18 posts

September 25, 2020 at 8:29 am

In reply to dave_59:

below is the master transaction

class eit_axi_master_transaction #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) extends uvm_sequence_item;
 
 /////////////////////////////////////////////////////////////////////////////// 
 // bit [(ADDR_WIDTH-1):0] Lower_value=0;
 // bit [(ADDR_WIDTH-1):0] Upper_value=`MAX_ADDR;
 //////////////////////////////////////////////////////////////////////////////
 
 //ADD_ID will be used as AWID & ARID in child write/read classes
  rand bit [3:0]ADD_ID;
 
 //DATA_ID will be used as form WID & RID in child write/read classes
  rand bit [3:0]DATA_ID;
 
  rand bit [(ADDR_WIDTH-1):0]ADDR;
  rand bit [7:0]LEN;
  rand bit [2:0]SIZE;
  rand bit [1:0]BURST;
 
 
 `uvm_object_param_utils_begin(eit_axi_master_transaction #(ADDR_WIDTH,DATA_WIDTH))
    `uvm_field_int(ADD_ID,UVM_ALL_ON)
    `uvm_field_int(DATA_ID,UVM_ALL_ON)
    `uvm_field_int(ADDR,UVM_ALL_ON)
    `uvm_field_int(LEN,UVM_ALL_ON)
    `uvm_field_int(SIZE,UVM_ALL_ON)
    `uvm_field_int(BURST,UVM_ALL_ON)
  `uvm_object_utils_end
 
  //---------------------------------------------------------------------------------------------------------------------------------------------
  // Constraint: This constraint help to work VIP as per specification
  // Provide ADDRESS range in MAX_ADDR_RANGE : User can give this address via test cases
  //---------------------------------------------------------------------------------------------------------------------------------------------
 
  //Constraint for MAX address generation
///////////////////////////////////////////////////////////////////////////////////
// constraint MAX_ADDR_RANGE {  ADDR inside {[Lower_value:Upper_value]};  }
  constraint MAX_ADDR_RANGE {  ADDR inside {[0:`MAX_ADDR]};  }
/////////////////////////////////////////////////////////////////////////////////
 
//Constraint for generating only INCR burst for LEN greater than 15
  constraint BURST_TYPE_cr {if (LEN > 'd15) BURST=='b01 ;}
 
//Constraint generating NOT generating Reserved type
  constraint BURST_NOT_BE_RESERVED_cr {BURST != 'b11;}
 
  constraint ADD_ID_DATA_ID_MATCH_cr {ADD_ID == DATA_ID ;}
 
//Constraint for generating Aligned addresses for Wrap burst
  constraint WRAP_CR{if(BURST=='b10)  ADDR ==int'(ADDR/2**SIZE)*(2**SIZE); LEN inside{1,3,7,15};  }
 
 
//Constraint for keeping generated data size less than or equal to dat-bus
  constraint SIZE_value_cr {2**SIZE <= (DATA_WIDTH/8) ;}
 
  function new(string name = "eit_axi_master_transaction");
    super.new(name);
  endfunction
endclass : eit_axi_master_transaction
 
 
/*------------------------Extended WRITE transaction class------------------------------*/
 class eit_axi_master_write_transaction #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) extends eit_axi_master_transaction #(ADDR_WIDTH,DATA_WIDTH);
 
  //---------------------------------------------------------------------------------------------------------------------------------------------
  // DATA and STROB are dynamic array because we have to genrate that based on the transfer size
  // Used WDATA constraint. It help to genrate random data as we required
  //---------------------------------------------------------------------------------------------------------------------------------------------
 
   rand bit [(DATA_WIDTH-1):0] WDATA[];
  rand bit [(DATA_WIDTH/8)-1:0] WSTRB[];
  bit[1:0] BRESP;
 
`uvm_object_param_utils_begin(eit_axi_master_write_transaction #(ADDR_WIDTH,DATA_WIDTH))
 
    `uvm_field_array_int(WDATA,UVM_ALL_ON|UVM_NOCOMPARE) //  no compare
    `uvm_field_array_int(WSTRB,UVM_ALL_ON|UVM_NOCOMPARE) //  no compare
    `uvm_field_int(BRESP,UVM_ALL_ON|UVM_NOCOPY|UVM_NOCOMPARE)  // no copy no compare
     `uvm_object_utils_end
 
  constraint WSTRB_size_cr {WSTRB.size() == 1 ;}
  // dynamic array size declaration  
 
   constraint WDATA_size_cr {WDATA.size() == LEN +1 ;}
 
  //array element has byte dependent upon size.
  constraint WDATA_element_size_cr { foreach( WDATA[i]) WDATA[i]<=((2**((2**SIZE)*8)-1));}
 
  function new(string name = "eit_axi_master_write_transaction");
    super.new(name);
  endfunction
 endclass : eit_axi_master_write_transaction
/*-------------------------------------------------------------------------------------*/
 
 
/*------------------------Extended READ transaction class------------------------------*/
 class eit_axi_master_read_transaction #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) extends eit_axi_master_transaction #(ADDR_WIDTH,DATA_WIDTH);
 
   //---------------------------------------------------------------------------------------------------------------------------------------------
  // DATA and RESP are dynamic array because we have to genrate that based on the transfer size
  //---------------------------------------------------------------------------------------------------------------------------------------------
 
  bit [(DATA_WIDTH-1):0] RDATA[];  
  bit [1:0] RRESP[];
 
 `uvm_object_param_utils_begin(eit_axi_master_read_transaction #(ADDR_WIDTH,DATA_WIDTH))
    `uvm_field_array_int(RDATA,UVM_ALL_ON|UVM_NOCOPY|UVM_NOCOMPARE) // no copy no compare
    `uvm_field_array_int(RRESP,UVM_ALL_ON|UVM_NOCOPY|UVM_NOCOMPARE)     // no copy no compare
  `uvm_object_utils_end
 
function new(string name = "eit_axi_master_read_transaction");
    super.new(name);
  endfunction
endclass : eit_axi_master_read_transaction
 
 /*-------------------------------------------------------------------------------------*/

Answer 3

Solution

dave_59

Forum Moderator

9459 posts

September 25, 2020 at 8:59 am

In reply to jj_bukhari:

These declarations are reversed:

eit_axi_master_read_transaction #(ADDR_WIDTH,DATA_WIDTH)  sq_transaction_w;
eit_axi_master_write_transaction #(ADDR_WIDTH,DATA_WIDTH) sq_transaction_r;

— Dave Rich, Verification Architect, Siemens EDA

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