hello, forum
I am getting the below error
Error-[SV-ICA] Illegal class assignment
axi_test_top.sv, 79
"this.sq_transaction_w = uvm_object_registry#($unit::eit_axi_master_write_transaction#(32,32),"<unknown>")::create("sq_transaction_w", this, /* contxt = "\000" */);"
Expression
'uvm_object_registry#($unit::eit_axi_master_write_transaction#(32,32),"<unknown>")::create("sq_transaction_w",
this, )' on rhs is not a class or a compatible class and hence cannot be
assigned to a class handle on lhs.
Please make sure that the lhs and rhs expressions are compatible.
Instance stack trace:
test_main#(32,32) testbench.sv, 19
testbench testbench.sv, 5
Error-[SV-ICA] Illegal class assignment
axi_test_top.sv, 80
"this.sq_transaction_r = uvm_object_registry#($unit::eit_axi_master_read_transaction#(32,32),"<unknown>")::create("sq_transaction_r", this, /* contxt = "\000" */);"
Expression
'uvm_object_registry#($unit::eit_axi_master_read_transaction#(32,32),"<unknown>")::create("sq_transaction_r",
this, )' on rhs is not a class or a compatible class and hence cannot be
assigned to a class handle on lhs.
Please make sure that the lhs and rhs expressions are compatible.
Instance stack trace:
test_main#(32,32) testbench.sv, 19
testbench testbench.sv, 5this is the testbench code
`include "interface.sv"
`include "axi_test_top.sv"
//TOP TESTBENCH
module testbench;
bit clk,reset;
parameter ADDR_WIDTH=32;
parameter DATA_WIDTH=32;
always #10 clk = ~clk;
initial begin
reset = 1;
end
eit_axi_interface #(.ADDR_WIDTH(ADDR_WIDTH),.DATA_WIDTH(DATA_WIDTH)) intf(clk,reset);
typedef test_main#(ADDR_WIDTH,DATA_WIDTH) test;
initial begin
//enable wave dump
uvm_config_db#(virtual eit_axi_interface#(.ADDR_WIDTH(ADDR_WIDTH),.DATA_WIDTH(DATA_WIDTH)))::set(uvm_root::get(),"*","intf",intf);
$dumpfile("dump.vcd");
$dumpvars;
end
//calling test
initial begin
run_test("test_main");
end
endmodulethis is the test code
`define MAX_ADDR 5000
`define READ_ONLY_STARTING_ADD 2000
`include "slave_memory.svh"
`include "slave_memory.sv"
`include "axi_slave_configuration.sv"
//`include "axi_master_configuration.sv"
`include "env_config.sv"
`include "axi_master_transaction.sv"
`include "axi_master_sequence.sv"
`include "axi_environment.sv"
//TEST CLASS
class test_main #(int ADDR_WIDTH=32,DATA_WIDTH=32) extends uvm_test;
//------------------------------------------
//register class to factory by name and by type both
//------------------------------------------
typedef uvm_component_registry #(test_main#(ADDR_WIDTH,DATA_WIDTH),"test_main") type_id;
static function type_id get_type();
return type_id::get();
endfunction:get_type
virtual function uvm_object_wrapper get_object_type();
return type_id::get();
endfunction:get_object_type
const static string type_name=$sformatf("test_main#(%0d,%0d)",ADDR_WIDTH,DATA_WIDTH);
virtual function string get_type_name();
return type_name;
endfunction:get_type_name
//environmnt config class instance
env_config#(ADDR_WIDTH,DATA_WIDTH) e_config;
//slave configuration configuration,class handle
axi_slave_configuration#(ADDR_WIDTH,DATA_WIDTH) slv_config;
//env & sequence instance
axi_env #(ADDR_WIDTH,DATA_WIDTH) env_obj;
master_write_generator_sequence #(ADDR_WIDTH,DATA_WIDTH) seq_w;
master_read_generator_sequence #(ADDR_WIDTH,DATA_WIDTH) seq_r;
eit_axi_master_transaction #(ADDR_WIDTH,DATA_WIDTH) sq_transaction;
eit_axi_master_read_transaction #(ADDR_WIDTH,DATA_WIDTH) sq_transaction_w;
eit_axi_master_write_transaction #(ADDR_WIDTH,DATA_WIDTH) sq_transaction_r;
// constructor
function new(string name = "test_main",uvm_component parent=null);
super.new(name,parent);
endfunction : new
//Build Phase
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
...
sq_transaction = eit_axi_master_transaction#(ADDR_WIDTH,DATA_WIDTH)::type_id::create("seq_item",this);
sq_transaction_w = eit_axi_master_write_transaction#(ADDR_WIDTH,DATA_WIDTH)::type_id::create("sq_transaction_w",this);//ERRORNEOUS LINE(HELP NEEDED HERE)
sq_transaction_r = eit_axi_master_read_transaction#(ADDR_WIDTH,DATA_WIDTH)::type_id::create("sq_transaction_r",this); //ERRORNEOUS LINE(HELP NEEDED HERE)
...
endfunction : build_phase
....
....
endclass : test_mainthis is the sequence file code
class master_write_generator_sequence #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) extends uvm_sequence;
`uvm_object_param_utils(master_write_generator_sequence #(ADDR_WIDTH,DATA_WIDTH))
// uvm_analysis_port #(eit_axi_master_write_transaction #(ADDR_WIDTH,DATA_WIDTH)) gen_scb_write;
eit_axi_master_write_transaction #(ADDR_WIDTH,DATA_WIDTH) trans_w,trans_w_scb;
//Constructor
function new(string name = "master_write_generator_sequence Created");
super.new(name);
endfunction
virtual task pre_body();
// gen_scb_write = new("gen_scb_write", this);
endtask
virtual task body();
// scb sending problem
trans_w = eit_axi_master_write_transaction#(ADDR_WIDTH,DATA_WIDTH)::type_id::create("Processes for genration of eit_axi_master_write_transaction request");
trans_w_scb = eit_axi_master_write_transaction#(ADDR_WIDTH,DATA_WIDTH)::type_id::create("Processes for genration of eit_axi_master_write_transaction request");
/// config class adition...........................
repeat(2)
begin
`uvm_do (trans_w);
trans_w_scb.copy(trans_w);
//gen_scb_write.write(trans_w_scb);
end
endtask
endclass
class sequencer_write#(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) extends uvm_sequencer;
`uvm_component_param_utils(sequencer_write #(ADDR_WIDTH,DATA_WIDTH))
//constructor
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
endclass
class master_read_generator_sequence #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) extends uvm_sequence;
`uvm_object_param_utils(master_read_generator_sequence #(ADDR_WIDTH,DATA_WIDTH))
// uvm_analysis_port #(eit_axi_master_read_transaction #(ADDR_WIDTH,DATA_WIDTH)) gen_scb_read;
eit_axi_master_read_transaction #(ADDR_WIDTH,DATA_WIDTH) trans_r,trans_r_scb;
//Constructor
function new(string name = "master_read_generator_sequence Created");
super.new(name);
endfunction
virtual task pre_body();
// gen_scb_read = new("gen_scb", this);
endtask
virtual task body();
// scb sending problem
trans_r = eit_axi_master_read_transaction#(ADDR_WIDTH,DATA_WIDTH)::type_id::create("Processes for genration of eit_axi_master_read_transaction request");
trans_r_scb = eit_axi_master_read_transaction#(ADDR_WIDTH,DATA_WIDTH)::type_id::create("Processes for genration of eit_axi_master_read_transaction request");
/// config class adition...........................
repeat(2)
begin
`uvm_do (trans_r);
trans_r_scb.copy(trans_r);
//gen_scb_read.write(trans_r_scb);
end
endtask
endclass
class sequencer_read#(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) extends uvm_sequencer;
`uvm_component_param_utils(sequencer_read #(ADDR_WIDTH,DATA_WIDTH));
//constructor
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
endclasscan anyone help?
Thanks & Regards
jj_bukhari
