Include vhdl package in system verilog

UVM
,
1

Hi,
I need to import a VHDL package into a SystemVerilog Environment.
How can I do it?

I tried to use in:
import package::*
`include “package.vhd”

and it’s not worked.

Thanks

2

In reply to tamarpanet:

There is no standard for interoperability between standards. Please check your tool’s User Manual or contact your vendor directly. This forum is not for tool specific issues.