Implementation of reg2bus() and bus2reg() methods

UVM
,
1

Hi,
I was trying to modify my “reg adapter” and “reg predictor” in such a way that it can support BURST access for my register model.
I have referred UVM COOKBOOK for the same and came across these statements “reg2bus - Overload to convert generic register access items to target bus agent sequence items” and “bus2reg - Overload to convert target bus sequence items to register model items” in page number 318 “Implementing an Adapter” section.

I know that the OOP concept of OVERLOADING is not supported by systemverilog, but the statements given are a bit contradictory pertaining to systemverilog language.

Out of curiosity I have just tried to overload the reg2bus() and bus2reg() in my new predictor, but errors were thrown.

Can you guys please clarify whether the meaning of the above statements are OVERLOAD or OVERRIDE.

Thanks,

–
Best Regards,
Neith

2

In reply to UVM Beginner:

Hi can Anyone reply to this query.

Thanks,
Neith

3

In reply to UVM Beginner:

I think they meant to say Override, as in “override a virtual method”. Some people mix up the two terms.

No one can help you with errors that you do not show.