In reply to chr_sue:
Thank you. It make sense.
Hope you have patience to help me/us to understand further. There're some students ramping up on UVM/system verilog, thus the topic is quite interesting from academycal perspective.
Apparently, the usage of connect phase seems to be strictly required, also when there's no specific top-down bottom-up requirement.
There's a simple design. There's one physical interface which is passed, through the config db at two components:
- test class
- virtual seqeuncer instantiated by the test class
uvm_config_db#(virtual tb_sv2uvm_if)::set(uvm_root::get() ,
The test gets the handle in the build phase (currently, which is wrong but works).
The vsqr has to get the handle in the connect phase (otherwise there's the error message of this thread).
One analomaly: the error message is fired by vsim when the first signal of the interface is accessed. Such line belongs to the first sequence executed by the vsqr.
I would have expected the error to be fired in the build phase where we were doing
`uvm_error("", "uvm_config_db::get - Failed")
In other words, why the get method works? Maybe the physical/virtual connection is done by vsim in the connect phase?