Packages must not contain any hierarchical references that reach outside the package. This is why SystemVerilog has virtual interface variables that can hold references to actual interface instances. If you need to access a something in a module, then you can use the bind construct to insert an indirect reference to your function. See this post and the link to my DVCon paper.
Hi,
I was struggling with the same issue.
My solution was to create an interface which is not inside a package.
From this interface you can call tasks, and those tasks can call RTL functions like:
`PATH_TO_RTL_MODEL_FUNCTION.function_name(input_1,output_1);
If you want to stimulate internal signals in your DUT you should do this using an additional agent. Because you have to synchronize this setting with the behavior of the other interfaces. In the driver of this agent you can call your function.
In reply to bassem yasser:
You should set this interface in you top_tb file with config_db.
Then get it from the driver. than you can call the function from the driver.
Aha , i got it , so if the interface instance for example vif_inst;
i will use vif_inst.function_name();
correct ?