I2C SCL generation for single master

UVM
, ,
1

i am doing the I2C verification , went through the NXP specification
if i take single master configuration
so in my master driver initially after the reset , both SCL and SDA is held high , after START sequence i make my SCL go low
next how to proceed with SCL generation and for STOP sequence again the SCL should be dragged HIGH

since this SCL is critical part controlling the operation
i want to know logic behind SCL generation for single master
is there any reference code wrt to SCL generation would be much helpful

Regards,
Divya

2

In reply to divya1988:

You should ask your i2c spec what happens with the SCL.
Your question is not UVM related.

3

I2C UVM example:
https://github.com/dovstamler/uvm_agents/tree/master/src/i2c

4

In reply to chr_sue:

I2C i am trying for my own understanding of writing UVM testbench for bus protocols
this SCL is generated by master it remains in high state till the START sequence is detected
once START is detected the scl will go low

next the 7 or 10 bit address are driven by master bit by bit whenever SCL is low and sampled by slave when SCL is high

so how to generate this SCL clock signal from the master driver (consider single master and single slave configuration )

i am asking logic

5

In reply to divya1988:

You need to know the SCL low and SCL high period and other timing related specs of I2C.

After START condition detection,you can give a delay of SCL low period and then rise SCL and put it high for SCL high period.Similarly you can do for STOP condition also.