I want to use vritual sequence to start a register_sequence ,what's wrong with my code?

Hi,all:
I want to start a register sequence by using virtual sequence,but when I pass a Pointer of regmodel from virtual sequencer to register sequence, ncvlog think it is not correct ,and I don’t know why. Here is my code :
virtual sequencer

class vsequencer extends uvm_sequencer;
   `uvm_component_utils(vsequencer)
     apb_master_sequencer   apb_seq;
     my_reg_block   regmodel;
     function new(string name,uvm_component parent);
         super.new(name,parent);
     endfunction
endclass:vsequencer

virtual sequence

 class  vsequence  extends uvm_sequence;
   `uvm_object_utils(vsequence)
   `uvm_declare_p_sequencer(vsequencer)
    my_reg_seq   reg_seq;
    function  new(string name="vsequence");
        super.new(name);
    endfunction : new
    virtual   task  body();
        reg_seq=my_reg_seq::type_id::create("reg_seq");
        reg_seq.regmodel=p_sequencer.regmodel;
        reg_seq.start(null);
    endtask : body
endclass : vsequence

test

class   my_reg_test  extends   uvm_test;
   `uvm_component_utils(my_reg_test)
    reg_tb   reg_tb0;
    function new(string name,uvm_component parent);
         super.new(name,parent);
    endfunction : new
    virtual function build_phase(uvm_phase phase);
         super.build_phase(phase);
         reg_tb0=reg_tb::type_id::create("reg_tb0",this);
         vsqr=vsequencer::type_id::create("vsqr",this):
         uvm_config_db#(uvm_object_wrapper)::set(this,"vsqr.run_phase","default_sequence",vsequence::type_id::get());
    endfunction : build_phase
    virtual function connect_phase(uvm_phase phase);
         vsqr.regmodel=reg_tb0.regmodel;
    endfunction : connect_phase
endclass : my_reg_test

And the nclog :
reg_seq.regmodel=p_sequencer.regmodel

ncvlog:E,NOTCLM(./my_reg/reg_seq_lib.sv,49|44):regmodel is not a class item.

Does anyone know ,how can I fix it?

You might want to check this:
`uvm_declare_p_sequencer(vsequence)

For simplicity sake, I would recommend avoiding macros, default_sequence method and using seq.start(sqr) type of syntax.

The default sequence use model for starting sequences is deprecated in the UVM.

Like the previous correspondent I’d advise using vseq.start() since that means you know what’s going on.

In your code you don’t show the content of the my_reg_seq class, from the error message you quote, it would seem to be missing handle for the register model.

In reply to mperyer:

here is my code of my_reg_seq:

class my_reg_seq extends uvm_reg_sequence;
    my_reg_block regmodel;
    `uvm_object_utils(my_reg_seq)
    function new(string name ="my_reg_seq");
        super.new(name);
    endfunction : new
    rand uvm_reg_addr_t addr;
    rand uvm_reg_data_t data;
    virtual task body();
        uvm_status_e status;
        if(starting_phase != null)
            starting_phase.raise_objection(this,{"Running sequence '"get_full_name(),"'"});
        addr=32'h0;
        data=32'h1;
        regmodel=my_reg_block::type_id::create("regmodel");
        repeat(10) begin
            regmodel.n_ram.write(status,addr,data,.parent(this));
            addr++;
            data += 32'h10;
        end
        if(starting_phase != null)
            starting_phase.drop_objection(this,{"Completed sequence '",get_full_name(),"'"});
    endtask : body
endclass : my_reg_seq

In your register sequence you have a line that creates a new version of the register model overriding the handle assignment from the virtual sequence. This version of register model is not “connected” into the rest of the UVM environment which probably accounts for the error.

If you remove this line it should work.

In reply to mperyer:

I tried ,but it does not work . It is the same error message.
For more information,here is my code of reg_tb.sv

`ifndef REG_TB
`define REG_TB

`include "my_config.sv"
`include "reg_req_lib.sv"
`include "ral_apb_reg_block.sv"

class reg_tb extends uvm_env;
    `uvm_component_utils(reg_tb)
    apb_env  apb0;
    my_config  cfg;
    my_reg_block regmodel;
    reg_to_apb_adapter  reg_sqr_adapter;
    reg_to_apb_adapter  mon_reg_adapter;
    uvm_reg_predictor#(apb_transfer) reg_predictor;
    
    function new(string name,uvm_component parent);
        super.new(name,parent);
    endfunction:new
    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        cfg=my_config::type_id::create("cfg");
        apb0=apb_env::type_id::create("apb0",this);
        uvm_config_object::set(this,"apb0*","cfg",cfg);
        uvm_config_object::set(this,"slave[0]*","cfg",cfg.slave_configs[0]);

        regmodel=my_reg_block::type_id::create("regmodel",,get_full_name());
        regmodel.configure(null,"top.u_dut.apb_slave");
        regmodel.build();
        regmodel.lock_model();
        regmodel.reset();
        reg_sqr_adapter=reg_to_apb_adapter::type_id::create("reg_sqr_adapter",,get_full_name());
        mon_reg_adapter=reg_to_apb_adapter::type_id::create("mon_reg_adapter",,get_full_name());
        reg_predictor=new("reg_predictor",this);
    endfunction : build_phase

    virtual function void connect_phase(uvm_phase phase);
        regmodel.default_map.set_sequencer(apb0.master.sequencer,reg_sqr_adapter);
        regmodel.default_map.set_auto_predict(1);
        reg_predictor.map=apb_slave.default_map;
        reg_predictor.adapter=mon_reg_adapter;
        apb0.master.monitor.item_collected_port.connect(reg_predictor.bus_in);
    endfunction:connect_phase
endclass : reg_tb
`endif

I think you have to use uvm_sequencer_utils instead of uvm_component_utils for vsequencer.
You might also need `uvm_update_sequence_lib macro in the constructor.

I still think now is the time to remove all these macros, simplify and use seq.start(vsqr).

I noticed in your last post that you are `including files rather than using package based name spaces.

Is your register sequence in the reg_req_lib.sv file? If so, it will be read before the register model, this may be the source of your problem.

If not, do you know which line in your register sequence gives the error message? It would help to share that information.

In reply to mperyer:

reg_seq.regmodel=p_sequencer.regmodel

ncvlog:E,NOTCLM(./my_reg/reg_seq_lib.sv,49|44):regmodel is not a class item.