Hi,all:
I want to start a register sequence by using virtual sequence,but when I pass a Pointer of regmodel from virtual sequencer to register sequence, ncvlog think it is not correct ,and I don’t know why. Here is my code :
virtual sequencer
class vsequencer extends uvm_sequencer;
`uvm_component_utils(vsequencer)
apb_master_sequencer apb_seq;
my_reg_block regmodel;
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
endclass:vsequencer
virtual sequence
class vsequence extends uvm_sequence;
`uvm_object_utils(vsequence)
`uvm_declare_p_sequencer(vsequencer)
my_reg_seq reg_seq;
function new(string name="vsequence");
super.new(name);
endfunction : new
virtual task body();
reg_seq=my_reg_seq::type_id::create("reg_seq");
reg_seq.regmodel=p_sequencer.regmodel;
reg_seq.start(null);
endtask : body
endclass : vsequence
test
class my_reg_test extends uvm_test;
`uvm_component_utils(my_reg_test)
reg_tb reg_tb0;
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction : new
virtual function build_phase(uvm_phase phase);
super.build_phase(phase);
reg_tb0=reg_tb::type_id::create("reg_tb0",this);
vsqr=vsequencer::type_id::create("vsqr",this):
uvm_config_db#(uvm_object_wrapper)::set(this,"vsqr.run_phase","default_sequence",vsequence::type_id::get());
endfunction : build_phase
virtual function connect_phase(uvm_phase phase);
vsqr.regmodel=reg_tb0.regmodel;
endfunction : connect_phase
endclass : my_reg_test
And the nclog :
reg_seq.regmodel=p_sequencer.regmodel
ncvlog:E,NOTCLM(./my_reg/reg_seq_lib.sv,49|44):regmodel is not a class item.
The default sequence use model for starting sequences is deprecated in the UVM.
Like the previous correspondent I’d advise using vseq.start() since that means you know what’s going on.
In your code you don’t show the content of the my_reg_seq class, from the error message you quote, it would seem to be missing handle for the register model.
In your register sequence you have a line that creates a new version of the register model overriding the handle assignment from the virtual sequence. This version of register model is not “connected” into the rest of the UVM environment which probably accounts for the error.
I think you have to use uvm_sequencer_utils instead of uvm_component_utils for vsequencer.
You might also need `uvm_update_sequence_lib macro in the constructor.
I still think now is the time to remove all these macros, simplify and use seq.start(vsqr).