can anyone please elaborate what is a BFM and how does it is used in verification with any good example or reference.
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In reply to Arun_Rajha:
https://verificationacademy.com/cookbook/testbench/integrationlevel
https://verificationacademy.com/forums/uvm/what-difference-between-driver-and-bfm
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In reply to dave_59:
Hi @dave_59
I dont have a RTL part of Memory or still the RTL team is working on that. So in these case, i have been told that a BFM has been used instead of the real RTL code. I have been told that in order to make sure that the transactions are fine in the memory i need to check a proprietary Bus connecting the memory and a module in my rtl. How do you define BFM here. As previously we meant BFM as subset of driver module which is a testbech component.
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In reply to Arun_Rajha:
It looks like your BFM is considered as a behavioral model of your DUT. If it has the same port connections as your RTL DUT will have you can instantiate this module in the toplevel of your testbench.
But note, even if the DUT does not exist, but you have all the functional intefaces/ports defiend you can develop and debug your UVM testbench.
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In reply to chr_sue:
In reply to Arun_Rajha:
It looks like your BFM is considered as a behavioral model of your DUT. If it has the same port connections as your RTL DUT will have you can instantiate this module in the toplevel of your testbench.
But note, even if the DUT does not exist, but you have all the functional intefaces/ports defiend you can develop and debug your UVM testbench.
yes i can debug with the help of interface or ports but my doubt here is does the bfm will mimic the working of entire memory(DUT which is not here in my case). If it mimics then how does it differs from the real memory(DUT).
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In reply to Arun_Rajha:
This depends on the quality of your BFM. If not all the functionality is implemented you cannot debug it.
If you do not have any DUT model you cannot investigate responses to DUT activities.
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