I am doing 64/66b encoder i got fatal error Fatal: (SIGSEGV) Bad handle or reference

UVM
,
1

I am doing a 64/66b encoder but i have got some error
** Note: (vsim-3813) Design is being optimized due to module recompilation…

Loading sv_std.std

Loading mtiUvm.uvm_pkg

Loading work.64to66varificatio_sv_unit

Loading work.top(fast)

Loading work.intf(fast)

Loading work.adder(fast)

Loading C:\questasim_10.0b\uvm-1.0p1\win32\uvm_dpi.dll

run -all

----------------------------------------------------------------

UVM-1.0p1

(C) 2007-2011 Mentor Graphics Corporation

(C) 2007-2011 Cadence Design Systems, Inc.

(C) 2006-2011 Synopsys, Inc.

----------------------------------------------------------------

UVM_INFO @ 0: reporter [RNTST] Running test base_test…

----rst started-----

----rst started-----

-------------------------------------------------------------------------------

Name Type Size Value

-------------------------------------------------------------------------------

tx seq_item - @667

begin_time time 64 10

depth int 32 'd2

parent sequence (name) string 3 seq

parent sequence (full name) string 32 uvm_test_top.env1.agent1.sqr.seq

sequencer string 28 uvm_test_top.env1.agent1.sqr

-------------------------------------------------------------------------------

** Fatal: (SIGSEGV) Bad handle or reference.

Time: 15 ns Iteration: 1 Process: /uvm_pkg::uvm_task_phase::execute File: 64to66varificatio.sv

Fatal error at 64to66varificatio.sv line 291

HDL call sequence:

Stopped at 64to66varificatio.sv 291

called from C:/questasim_10.0b/win32/…/verilog_src/uvm-1.0p1/src/base/uvm_phases.svh 583

called from C:/questasim_10.0b/win32/…/verilog_src/uvm-1.0p1/src/base/uvm_phases.svh 2788

quit -sim

varification code

interface intf(input logic clk,rst);
logic [63:0] txd;
logic [7:0] txc;
logic [65:0] entxd;
logic [1:0]sync;
logic [7:0] data0;
logic [7:0] data1;
logic [7:0] data2;
logic [7:0] data3;
logic [7:0] data4;
logic [7:0] data5;
logic [7:0] data6;
logic [7:0] data7;
logic [6:0]control0;
logic [6:0]control1;
logic [6:0]control2;
logic [6:0]control3;
logic [6:0]control4;
logic [6:0]control5;
logic [6:0]control6;
logic [6:0]control7;
logic [63:0] txd1;
endinterface

module adder(intf inf);

always @(inf.txd)
begin
inf.control0=inf.txd[14:8];
inf.control1=inf.txd[21:15];
inf.control2=inf.txd[28:22];
inf.control3=inf.txd[35:29];
inf.control4=inf.txd[42:36];
inf.control5=inf.txd[49:43];
inf.control6=inf.txd[56:50];
inf.control7=inf.txd[63:57];
inf.data0=inf.txd[7:0];
inf.data1=inf.txd[15:8];
inf.data2=inf.txd[23:16];
inf.data3=inf.txd[31:24];
inf.data4=inf.txd[39:32];
inf.data5=inf.txd[47:40];
inf.data6=inf.txd[55:48];
inf.data7=inf.txd[63:56];
inf.txd1=inf.txd;
end

always @ (posedge inf.clk)
begin
if(inf.rst==1)
inf.entxd=66’b0;

else if(inf.txc==16'h00)
  begin
  inf.sync=01;
  inf.entxd={inf.data7,inf.data6,inf.data5,inf.data4,inf.data3,inf.data2,inf.data1,inf.data0,inf.sync};
end
else if(inf.txc==16'hff)
  begin
    inf.sync=10;
    inf.txd1[7:0]=16'h1e;
    inf.entxd={inf.control7,inf.control6,inf.control5,inf.control4,inf.control3,inf.control2,inf.control1,inf.control0,inf.txd1[7:0] ,inf.sync};
  end
  else if(inf.txc==16'h01)
    begin
      inf.sync=10;
      inf.entxd={inf.data7,inf.data6,inf.data5,inf.data4,inf.data3,inf.data2,inf.data1,16'h78,inf.sync};
    end
  else if(inf.txc==16'hf1)
    begin
      inf.sync=10;
      inf.txd1[66:39]=28'b0;
      inf.entxd={inf.txd1[66:39],inf.txd[38:34],inf.data3,inf.data2,inf.data1,16'h4b,inf.sync};
    end
    else if(inf.txc==16'hff)
    begin
      inf.sync=10;
      inf.txd1[16:10]=7'b0000000;
      inf.entxd={inf.control7,inf.control6,inf.control5,inf.control4,inf.control3,inf.control2,inf.control1,inf.txd1[16:10],16'h87,inf.sync};
    end
    else if(inf.txc==16'hfe)
    begin
      inf.sync=10;
      inf.txd1[23:18]=6'b000000;
      inf.entxd={inf.control7,inf.control6,inf.control5,inf.control4,inf.control3,inf.control2,inf.txd1[23:18],inf.data0,16'h99,inf.sync};
    end
    else if(inf.txc==16'hfc)
    begin
      inf.sync=10;
      inf.txd1[30:26]=5'b00000;
      inf.entxd={inf.control7,inf.control6,inf.control5,inf.control4,inf.control3,inf.txd1[30:26],inf.data1,inf.data0,16'haa,inf.sync};
    end
    else if(inf.txc==16'hf8)
    begin
      inf.sync=10;
      inf.txd1[37:34]=4'b0000;
      inf.entxd={inf.control7,inf.control6,inf.control5,inf.control4,inf.txd1[37:34],inf.data2,inf.data1,inf.data0,16'hb4,inf.sync};
    end
    else if(inf.txc==16'hf0)
    begin
      inf.sync=10;
      inf.txd1[44:42]=3'b000;
      inf.entxd={inf.control7,inf.control6,inf.control5,inf.txd1[44:42],inf.data3,inf.data2,inf.data1,inf.data0,16'hcc,inf.sync};
    end
    else if(inf.txc==16'he0)
    begin
      inf.sync=10;
      inf.txd1[51:50]=2'b00;
      inf.entxd={inf.control7,inf.control6,inf.txd1[51:50],inf.data4,inf.data3,inf.data2,inf.data1,inf.data0,16'hd2,inf.sync};
    end
    else if(inf.txc==16'hc0)
    begin
      inf.sync=10;
      inf.txd1[58]=1'b0;
      inf.entxd={inf.control7,inf.txd1[58],inf.data5,inf.data4,inf.data3,inf.data2,inf.data1,inf.data0,16'he1,inf.sync};
    end
    else if(inf.txc==16'h80)
    begin
      inf.sync=10;
      
      inf.entxd={inf.data6,inf.data5,inf.data4,inf.data3,inf.data2,inf.data1,inf.data0,16'hd2,inf.sync};
    end
  end
endmodule
    
    
    
    `include "uvm_macros.svh"

import uvm_pkg::*;
class seq_item extends uvm_sequence_item;
`uvm_object_utils(seq_item)
rand bit [63:0]txd;
rand bit [7:0] txc;
bit [65:0] entxd;

     bit [1:0]sync;

bit [7:0] data0;
bit [7:0] data1;
bit [7:0] data2;
bit [7:0] data3;
bit [7:0] data4;
bit [7:0] data5;
bit [7:0] data6;
bit [7:0] data7;
bit [6:0]control0;
bit [6:0]control1;
bit [6:0]control2;
bit [6:0]control3;
bit [6:0]control4;
bit [6:0]control5;
bit [6:0]control6;
bit [6:0]control7;
bit [63:0] txd1;
bit clk;
bit rst;

 function new(string name="seq_item");
	 super.new(name);
 endfunction
  endclass
  
  
  
  class base_seq extends uvm_sequence#(seq_item);

seq_item tx;
`uvm_object_utils(base_seq)

function new(string name=“base_seq”);
super.new(name);
endfunction

 task body();

  repeat(2) begin
    
   tx=seq_item::type_id::create("tx");
   
   start_item(tx);
    assert(tx.randomize);
    tx.print();
   finish_item(tx);
  end

 endtask

endclass

class sequencer extends uvm_sequencer#(seq_item);

 `uvm_component_utils(sequencer)

 function new(string name,uvm_component parent);
     super.new(name,parent);
 endfunction

endclass

class driver extends uvm_driver#(seq_item);
seq_item tx;

virtual intf vif;

 `uvm_component_utils(driver)

 function new(string name,uvm_component parent);
     super.new(name,parent);
 endfunction

function void build_phase(uvm_phase phase);
void’(uvm_config_db #(virtual intf)::get(this,“”,“pif”,vif));
endfunction

 task run_phase(uvm_phase phase);
    wait(vif.rst);
$display("----rst started-----");
vif.entxd = 0;


wait(!vif.rst);

     forever begin
         seq_item_port.get_next_item(tx);
            vif.txd=tx.txd;
            vif.txc=tx.txc;
            vif.txd1=tx.txd1;
            vif.data0=tx.data0;
            vif.data1=tx.data1;
            vif.data2=tx.data2;
            vif.data3=tx.data3;
            vif.data4=tx.data4;
            vif.data5=tx.data5;
            vif.data6=tx.data6;
            vif.data7=tx.data7;
            vif.control0=tx.control0;
            vif.control1=tx.control1;
            vif.control2=tx.control2;
            vif.control3=tx.control3;
            vif.control4=tx.control4;
            vif.control5=tx.control5;
            vif.control6=tx.control6;
            vif.control7=tx.control7;
            
            @(negedge vif.clk); 
         seq_item_port.item_done();

     end
 endtask

endclass

class monitor extends uvm_monitor;
virtual intf vif;
seq_item tx;
uvm_analysis_port#(seq_item) port;

`uvm_component_utils(monitor)

function new(string name,uvm_component parent);

     super.new(name,parent);

endfunction

function void build_phase(uvm_phase phase);
void’(uvm_config_db#(virtual intf)::get(this,“”,“pif”,vif));
port=new(“port”,this);
tx=seq_item::type_id::create(“tx”);

endfunction

task run_phase(uvm_phase phase);
wait(vif.rst);
$display(“----rst started-----”);
vif.entxd = 0;

wait(!vif.rst);
 forever begin
   @(posedge vif.clk);
   tx.txd=vif.txd; 
   tx.txc=vif.txc; 
   tx.txd1=tx.txd1;
            tx.data0=vif.data0;
            tx.data1=vif.data2;
            tx.data2=vif.data3;
           tx.data3=vif.data4;
            tx.data4=vif.data5;
            tx.data5=vif.data6;
            tx.data6=vif.data7;
           tx.data7=vif.data8;
            tx.control0=vif.control0;
            tx.control1=vif.control1;
            tx.control2=vif.control2;
            tx.control3=vif.control3;
            tx.control4=vif.control4;
           tx.control5=vif.control5;
            tx.control6=vif.control6;
            tx.control7=vif.control7;
            
   
    @(negedge vif.clk); 
   vif.entxd=tx.entxd; 
   port.write(tx);

      
    


 end

endtask

endclass

  class agent extends uvm_agent;
 sequencer sqr;
 driver dvr;
 monitor mon;
 `uvm_component_utils(agent)

 function new(string name,uvm_component parent);
     super.new(name,parent);
 endfunction
 function void build_phase(uvm_phase phase);
     sqr=sequencer::type_id::create("sqr",this);
     dvr=driver::type_id::create("dvr",this);
     mon=monitor::type_id::create("mon",this);
 endfunction
 function void connect_phase(uvm_phase phase);
 
     dvr.seq_item_port.connect(sqr.seq_item_export);
 endfunction

endclass

class scoreboard extends uvm_scoreboard;
seq_item tx;
uvm_analysis_imp#(seq_item,scoreboard) imp;
bit [65:0]entxd;

`uvm_component_utils(scoreboard)

function new(string name,uvm_component parent);
super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
imp=new(“imp”,this);
tx=seq_item::type_id::create(“tx”);

endfunction

function void write(seq_item tx);
this.tx=tx;
if(tx.rst==1)
begin
tx.entxd=66’b0;
if(entxd==tx.entxd)
$display( “Result match”,“tx.entxd=%0d & entxd=%0d $time=%t”,tx.entxd,entxd,$time);
else
$display( “Result misMatch”,“tx.entxd=%0d & entxd=%0d $time=%t”,tx.entxd,entxd,$time);
end

   else if(tx.txc==16'h00)
  begin
  tx.sync=01;
  tx.entxd={tx.data7,tx.data6,tx.data5,tx.data4,tx.data3,tx.data2,tx.data1,tx.data0,tx.sync};
  if(entxd==tx.entxd)
    	$display( "Result match","tx.entxd=%0d & entxd=%0d   $time=%t",tx.entxd,entxd,$time);
	    else
  		$display( "Result misMatch","tx.entxd=%0d &  entxd=%0d  $time=%t",tx.entxd,entxd,$time);


    
end

else if(tx.txc==16’hff)
begin
tx.sync=10;
tx.txd1[7:0]=16’h1e;
tx.entxd={tx.control7,tx.control6,tx.control5,tx.control4,tx.control3,tx.control2,tx.control1,tx.control0,tx.txd1[7:0] ,tx.sync};
if(entxd==tx.entxd)
$display( “Result match”,“tx.entxd=%0d & entxd=%0d $time=%t”,tx.entxd,entxd,$time);
else
$display( “Result misMatch”,“tx.entxd=%0d & entxd=%0d $time=%t”,tx.entxd,entxd,$time);

  end
  else if(tx.txc==16'h01)
  begin
    tx.sync=10;
    
    tx.entxd={tx.data7,tx.data6,tx.data5,tx.data4,tx.data3,tx.data2,tx.data1,16'h78,tx.sync};
           if(entxd==tx.entxd)
    	$display( "Result match","tx.entxd=%0d & entxd=%0d   $time=%t",tx.entxd,entxd,$time);
	    else
  		$display( "Result misMatch","tx.entxd=%0d &  entxd=%0d  $time=%t",tx.entxd,entxd,$time);


  end
  else if(tx.txc==16'hf1)
  begin
    tx.sync=10;
    
    tx.txd1[66:39]=28'b0;
      tx.entxd={tx.txd1[66:39],tx.txd[38:34],tx.data3,tx.data2,tx.data1,16'h4b,tx.sync};
           if(entxd==tx.entxd)
    	$display( "Result match","tx.entxd=%0d & entxd=%0d   $time=%t",tx.entxd,entxd,$time);
	    else
  		$display( "Result misMatch","tx.entxd=%0d &  entxd=%0d  $time=%t",tx.entxd,entxd,$time);


  end
  
   else if(tx.txc==16'hff)
  begin
    tx.sync=10;
    
    tx.txd1[16:10]=7'b0000000;
      tx.entxd={tx.control7,tx.control6,tx.control5,tx.control4,tx.control3,tx.control2,tx.control1,tx.txd1[16:10],16'h87,tx.sync};

           if(entxd==tx.entxd)
    	$display( "Result match","tx.entxd=%0d & entxd=%0d   $time=%t",tx.entxd,entxd,$time);
	    else
  		$display( "Result misMatch","tx.entxd=%0d &  entxd=%0d  $time=%t",tx.entxd,entxd,$time);
end
else if(tx.txc==16'hfe)
  begin
    tx.sync=10;
    
    tx.txd1[23:18]=6'b000000;
      tx.entxd={tx.control7,tx.control6,tx.control5,tx.control4,tx.control3,tx.control2,tx.txd1[23:18],tx.data0,16'h99,tx.sync};
           if(entxd==tx.entxd)
    	$display( "Result match","tx.entxd=%0d & entxd=%0d   $time=%t",tx.entxd,entxd,$time);
	    else
  		$display( "Result misMatch","tx.entxd=%0d &  entxd=%0d  $time=%t",tx.entxd,entxd,$time);
end
else if(tx.txc==16'hfc)
  begin
    tx.sync=10;
    
    tx.txd1[30:26]=5'b00000;
      tx.entxd={tx.control7,tx.control6,tx.control5,tx.control4,tx.control3,tx.txd1[30:26],tx.data1,tx.data0,16'haa,tx.sync};
           if(entxd==tx.entxd)
    	$display( "Result match","tx.entxd=%0d & entxd=%0d   $time=%t",tx.entxd,entxd,$time);
	    else
  		$display( "Result misMatch","tx.entxd=%0d &  entxd=%0d  $time=%t",tx.entxd,entxd,$time);
end
 else if(tx.txc==16'hf8)
  begin
    tx.sync=10;
    
    tx.txd1[37:34]=4'b0000;
      tx.entxd={tx.control7,tx.control6,tx.control5,tx.control4,tx.txd1[37:34],tx.data2,tx.data1,tx.data0,16'hb4,tx.sync};
                   if(entxd==tx.entxd)
    	$display( "Result match","tx.entxd=%0d & entxd=%0d   $time=%t",tx.entxd,entxd,$time);
	    else
  		$display( "Result misMatch","tx.entxd=%0d &  entxd=%0d  $time=%t",tx.entxd,entxd,$time);
end
else if(tx.txc==16'hf0)
  begin
    tx.sync=10;
    
   tx.txd1[44:42]=3'b000;
      tx.entxd={tx.control7,tx.control6,tx.control5,tx.txd1[44:42],tx.data3,tx.data2,tx.data1,tx.data0,16'hcc,tx.sync};

                   if(entxd==tx.entxd)
    	$display( "Result match","tx.entxd=%0d & entxd=%0d   $time=%t",tx.entxd,entxd,$time);
	    else
  		$display( "Result misMatch","tx.entxd=%0d &  entxd=%0d  $time=%t",tx.entxd,entxd,$time);
end
  else if(tx.txc==16'he0)
  begin
    tx.sync=10;
    
   tx.txd1[51:50]=2'b00;
      tx.entxd={tx.control7,tx.control6,tx.txd1[51:50],tx.data4,tx.data3,tx.data2,tx.data1,tx.data0,16'hd2,tx.sync};

                   if(entxd==tx.entxd)
    	$display( "Result match","tx.entxd=%0d & entxd=%0d   $time=%t",tx.entxd,entxd,$time);
	    else
  		$display( "Result misMatch","tx.entxd=%0d &  entxd=%0d  $time=%t",tx.entxd,entxd,$time);
end

else if(tx.txc==16'hc0)
  begin
    tx.sync=10;
    
   tx.txd1[58]=1'b0;
      tx.entxd={tx.control7,tx.txd1[58],tx.data5,tx.data4,tx.data3,tx.data2,tx.data1,tx.data0,16'he1,tx.sync};

                   if(entxd==tx.entxd)
    	$display( "Result match","tx.entxd=%0d & entxd=%0d   $time=%t",tx.entxd,entxd,$time);
	    else
  		$display( "Result misMatch","tx.entxd=%0d &  entxd=%0d  $time=%t",tx.entxd,entxd,$time);
end
else if(tx.txc==16'h80)
  begin
    tx.sync=10;
    
   tx.entxd={tx.data6,tx.data5,tx.data4,tx.data3,tx.data2,tx.data1,tx.data0,16'hd2,tx.sync};

                   if(entxd==tx.entxd)
    	$display( "Result match","tx.entxd=%0d & entxd=%0d   $time=%t",tx.entxd,entxd,$time);
	    else
  		$display( "Result misMatch","tx.entxd=%0d &  entxd=%0d  $time=%t",tx.entxd,entxd,$time);
end

endfunction

endclass

class env extends uvm_env;
agent agent1;
scoreboard sb;

 `uvm_component_utils(env)

 function new(string name,uvm_component parent);
     super.new(name,parent);
 endfunction



 function void build_phase(uvm_phase phase);
     agent1=agent::type_id::create("agent1",this);
     sb=scoreboard::type_id::create("sb",this);
     
 endfunction

 function void connect_phase(uvm_phase phase);
         agent1.mon.port.connect(sb.imp);
         
 endfunction

endclass

class base_test extends uvm_test;
env env1;
base_seq seq;

 `uvm_component_utils(base_test)

 function new(string name,uvm_component parent);
     super.new(name,parent);
 endfunction
 function void build_phase(uvm_phase phase);
     env1=env::type_id::create("env1",this);
     seq=base_seq::type_id::create("seq");
 endfunction



 task run_phase(uvm_phase phase);
   phase.raise_objection(this);

   // $display(top.dut.pif.a);
    

    seq.start(env1.agent1.sqr);
     
   phase.drop_objection(this);

 endtask

endclass

//package v;
import uvm_pkg::*;
`include “uvm_macros.svh”
//endpackage:v
module top;

bit rst;
bit clk;
intf pif(clk,rst);

adder dut(pif);

initial begin
void’(uvm_config_db#(virtual intf)::set(uvm_root::get,“*”,“pif”,pif));
//run_test(“base_test”);
run_test(“base_test”);
end

initial begin
clk=0;
rst=1;
#10;
rst=0;
forever #5 clk=~clk;
end
endmodule

I am not able to understant what exactly error in code
please help me

2

In reply to taufeeq_khan:

I highly recommend that you put your environment on EDA Playground as it is easier to share, instead of posting a wall of code.

You will also be able to use newer versions of UVM as the version you are using is very old and may not support all features.

Initial analysis shows your monitor referencing ‘vif.data8’, which doesn’t exist in the interface. There are likely other errors as well, but this is the first one to appear.

3

In reply to cgales:
thanks for reply
I have corrected vif.data8 error but now output is not generating

** Note: (vsim-3813) Design is being optimized due to module recompilation…

Loading sv_std.std

Loading mtiUvm.uvm_pkg

Loading work.64to66varificatio_sv_unit

Loading work.top(fast)

Loading work.intf(fast)

Loading work.adder(fast)

Loading C:\questasim_10.0b\uvm-1.0p1\win32\uvm_dpi.dll

run -all

----------------------------------------------------------------

UVM-1.0p1

(C) 2007-2011 Mentor Graphics Corporation

(C) 2007-2011 Cadence Design Systems, Inc.

(C) 2006-2011 Synopsys, Inc.

----------------------------------------------------------------

UVM_INFO @ 0: reporter [RNTST] Running test base_test…

----rst started-----

----rst started-----

-------------------------------------------------------------------------------

Name Type Size Value

-------------------------------------------------------------------------------

tx seq_item - @667

begin_time time 64 10

depth int 32 'd2

parent sequence (name) string 3 seq

parent sequence (full name) string 32 uvm_test_top.env1.agent1.sqr.seq

sequencer string 28 uvm_test_top.env1.agent1.sqr

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

Name Type Size Value

-------------------------------------------------------------------------------

tx seq_item - @696

begin_time time 64 20

depth int 32 'd2

parent sequence (name) string 3 seq

parent sequence (full name) string 32 uvm_test_top.env1.agent1.sqr.seq

sequencer string 28 uvm_test_top.env1.agent1.sqr

-------------------------------------------------------------------------------

UVM_INFO verilog_src/uvm-1.0p1/src/base/uvm_objection.svh(1116) @ 30: reporter [TEST_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase

— UVM Report Summary —

4

In reply to taufeeq_khan:

What do you mean by “output is not generating”? I see two transactions being created by your sequence, which is exactly what you designed? You need to trace through your code and determine what is happening.

Also, you should never use $display() statements in a UVM testbench. Use the appropriate `uvm_* messaging macros as they make debugging easier.