How to write Predictor Model in UVM structure?

I have been working on a verification model of an american car tail light controller RTL. UVM structure has all the necessary VC’s including scoreboard. I need to discuss, what should be the predictor function in this case to check the integrity of scoreboard and compare with the actual data of DUT with the expected data?

 module carlights(
                  				// Input
                  				clk,
                  				rst,
                  				br,		
                  				lf,
						rt,
						haz,
					        // Outputs
                  				lights
                  				);


/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
// Input Declaration
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
  input         clk;
  input         rst;
  input         br;
  input         lf;
  input         rt;
  input 	haz;
 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
// Output Declaration
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
  output [5:0] lights;
 
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
// Internal Registers Declaration
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
reg Break ;     
reg Left  ;     
reg Right ;     
reg Hazard;     

reg [5:0]left_out;	//Lights flags on indicators
reg [5:0]right_out;
reg [5:0]haz_out;
reg [3:0] left_state;
reg [5:0]lights;

/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
// Internal Wires Declaration
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
wire  f_break,f_left, f_right, f_haz, f_break_rt, f_break_left;   
wire Flash_pattern ;
wire all_off ;  
wire ff_haz; 
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
/*++++++++++++++++++++++++++++++++++++++++++++++ MULTIPLEXER I/O +++++++++++++++++++++++++++++++++++++++++++++++++*/
/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
//--------- Break << Left << Right << Hazard ----------//
  
 assign  f_break 			= (br)&(~lf)&(~rt)&(~haz);
 assign  f_left 			= (~br)&(lf)&(~rt)&(~haz);
 assign  f_right 			= (~br)&(~lf)&(rt)&(~haz);
 assign  f_haz		 		= (~br)&(~lf)&(~rt)&(haz);
 assign  f_break_rt			= (br)&(~lf)&(rt)&(~haz);
 assign  f_break_left			= (br)&(lf)&(~rt)&(~haz);
 assign  all_off			= (~br)&(~lf)&(~rt)&(~haz);
 assign  ff_haz 			= ((~f_break)&(~f_left)&(~f_right)&(~f_break_rt)&(~f_break_left)&(~all_off))|(f_haz);		//consistant hazard flashing-none other signal 		

always@(*)
 begin
case ({f_break,f_left,f_right,ff_haz,f_break_rt,f_break_left})    
 //6'b000000: lights <=6'b000000; //this might be a problem
 6'b100000: lights <=6'b111111;
 6'b010000: lights <=left_out;
 6'b001000: lights <={3'b000,left_out[3],left_out[4],left_out[5]} ; //right_out 
 6'b000100: lights <=haz_out;
 6'b000010: lights <={3'b111,left_out[3],left_out[4],left_out[5]} ;//break_right_out;
 6'b000001: lights <={left_out[5:3],3'b111};	//break_left_out;
endcase
end

assign Flash_pattern =(f_left|f_right|f_break_rt|f_break_left); 
 //////////////////////
 //FSM
 //////////////
 // left_out block 
 always@(posedge clk or rst)
 begin
 if(rst)
 begin
 left_state <=4'b0000;
 left_out   <=6'b000000;
 end 
 else //if(f_left|f_right|f_break_rt|f_break_left)
 begin
 	 
 	//"left_state" is basically counter type thing (just bit 1 shifting) just adding at every iteration
 	//Flashing pattern is defined here
  case (left_state)
  4'b0000: begin
        left_out<=6'b000000;
        if(Flash_pattern)
        left_state <=4'b0001; 
        else 
        left_state <=4'b0000; 
  	     end 
	4'b0001: begin
  					left_out<=6'b001000;
  					left_state <=4'b0010; 
  					end   					
  4'b0010: begin
  					left_out<=6'b011000;
  					left_state <=4'b0100; 
  					end 
  4'b0100: begin
  					left_out<=6'b111000;
  					left_state <=4'b1000; 
  					end   	
  4'b1000: begin
  					left_out<=6'b000000;
  					left_state <=4'b0001; 
  					end  
  default: begin
  					left_out<=6'b000000;
  					left_state <=4'b0000;
  					end  
 								  					  					
 endcase
 end
 end 
// haz  block 
always@(posedge clk or posedge rst)
 begin
 if(rst)
 haz_out <=6'b000000;
 else begin 
 haz_out <= 6'b111111;
 if(ff_haz)
 haz_out <=~ haz_out;
 end 
 end
endmodule