How to write the assertion to check whether the 2 clock are synchronous or not?

Assertion to check whether 2 clock are synchronous or not?

In reply to abhi.khati7274:

Seems like you are interviewing for the same position as this person:

https://verificationacademy.com/forums/systemverilog/considering-there-are-two-clocks.-how-check-if-they-are-synchronous-using-assertions

In reply to dave_59:

Hello dave ,
Is there better way to write,i have written the code and its working as per my intention.

`timescale 1ns/100ps
module top;
  `define clk_period 10
  `define half_period 5
  
  bit clk1,clk2;
  
  
  always 
    begin
      # `half_period clk1=~clk1;
    end
  
  always 
    begin
      # `half_period clk2=~clk2;
    end
  
  initial begin
    $dumpfile("dump.vcd"); $dumpvars;
    #500;
    $finish();
  end  
  
  property check1;
    realtime var1;
    @(posedge clk1)
    (1,var1=$realtime) |=>(`clk_period==$realtime-var1);
  endproperty
  
    property check2;
    realtime var2;
      @(posedge clk2)
      (1,var2=$realtime) |=>(`clk_period==$realtime-var2);
  endproperty
  
  property check_sync;
    @(posedge clk1) !$rose(clk2);
  endproperty
  
  /*check_freq: assert property(check1)
    $display("%t check freq1 : clk1 freq matches",$time);
    else
      $warning("%t check freq : clk1 freq  doesnt matches",$time);
      
    check_freq2: assert property(check2)
      $display("%t check freq2 : clk2 freq matches",$time);
    else
      $warning("%t check freq : clk2 freq  doesnt matches",$time);*/
      
      check_freq_sync: assert property(check_sync)
        $display("%t check synch: clk1 and clk2 are in sync",$time);
        else
          $warning("%t check sync :clk1 and clk2 are not in sync", $time);
      
      endmodule

Hi Dave,
This link is broken. It doesn’t take us to to a intended page. Could you please re-share the correct link?

Regards

In reply to mahajana:

Sorry, that post seems to be deleted. It was the exact same question.

Hi Dave,
Thanks for letting me know. Is it possible to share the assertions which should be in place for checking such clocks? Lets say one is tb modelled clk(meant to check the rtl clk being generated in design) and the other one is actual rtl clk (which is supposed to be checked).

Please let me know your thoughts.

Regards

In reply to abhi.khati7274:
The simplest way to check.


 property check_sync;
    @(clk1) clk1 == clk2;
  endproperty

Thanks Dave.
I have written a few assertions like duty cycle, time period, etc. Will put sync one too as you suggested. Please let me know if more assertions need to be written to check modelled vs rtl clk.

Regards