How to write assertion check for signal change from non_zero value to zero value

UVM
1

I’m trying to create an assertion check for whenever signal A changes from non_zero value to zero value, next cycle B should be stable for 5cycles. Thanks

2

In reply to chendhu:
Coulsd you please show what you are trying?
BTW assertion know only logic high or low.

3

Hi

I have two signals
[2:0] ctrl;
en;
If I randomized ctrl signal it generates 0 to 7 values, Whenever ctrl signal changes from non_zero value(1,2…7) to zero(0)value, Next cycle en should be high for 5 clock cycles.
I need to check above condition.Thanks

4

In reply to chendhu:
You could try

$fell(ctrl) |=> ##5 en ##1 !en;

5

In reply to chendhu:

Try this,

property ctrl_en; (I assume its not a synchronous signal)
((ctrl==0) |-> ##1 $rose(en) [*5]);
endproperty
en_ctr: assert property(ctrl_en);

6

In reply to sai_pra99:

This wont work as $rose will not be repeated 5 times.



property cntrl_en ;
//clocking or  infer the default clocking 
(1,cntrl==0) |=> $rose(en) ##0 en[*5] ;

endproperty