How to write and read register in RAL

UVM
1

Hello,

My register model looks be generated normally.
The build phase in env was


regmodel = ral_block_cfg_regmodel::type_id::create("regmodel", this);
regmodel.build();
regmodel.default_map.set_base_addr('h11da00f0);
regmodel.add_hdl_path("TEST_TOP.xCORE.xCFG");
regmodel.lock_model();
regmodel.print();
uvm_config_db#(ral_block_cfg_regmodel)::set(this, "agnt", "regmodel", regmodel);

The RAL sequence is


task ral_seq::body();
  seq_item my_item;
  my_item = new();

  begin
    uvm_status_e status;
    uvm_reg_data_t data;

    regmodel.CFG.U20H0_BCFG.write(status, 32'h1234_5678);
    regmodel.CFG.U20H0_BCFG.read(status, data);
    regmodel.CFG.U20H0_PCFG.write(status, 32'hfedc_ba98);
    regmodel.CFG.U20H0_PCFG.read(status, data);
  end
endtask

However, the log was


UVM_INFO hsio_driver.sv(17) @4100: reporter [reg_adapter] reg2bus" addr = 11da00f0, data = 12345678 kind=0
UVM_INFO hsio_driver.sv(17) @4100: reporter [reg_adapter] reg2bus" addr = 11da00f0, data = 00000000 kind=1
UVM_INFO hsio_driver.sv(17) @4100: reporter [reg_adapter] reg2bus" addr = 11da00f4, data = fedcba98 kind=0
UVM_INFO hsio_driver.sv(17) @4100: reporter [reg_adapter] reg2bus" addr = 11da00f4, data = 00000000 kind=1

The read did not work, also the write/read was performed at the same time without time elapsing.
Please some tips for debugging.
Thanks.

2

In reply to uvmbee:

A few remarks:
(1) the regmodel is not a uvm_component. It does not belong to the topology of the UVM environment.
(2) The command lock_model should belong to your regmodel definition.
(3) Commonly you should create your regmodel in the base test class and pass it to an configuration object. This allows you to retrieve it in any place you need it.
(4) the regmodel object has to be part of your RAL sequence.

Please make these adoptions and retry running the RAL sequence.

3

In reply to chr_sue:

Thank you.

The register model report screen shot.
[Screenshot-aa hosted at ImgBB — ImgBB]](Screenshot-aa hosted at ImgBB — ImgBB])

But when I read those two address, those are zero, not reset value.
Screen shot
[Screenshot-bb hosted at ImgBB — ImgBB]](Screenshot-bb hosted at ImgBB — ImgBB])

4

In reply to uvmbee:

I do not see your UVM topology. One thing is strange:
Where do you have the uvm_adapter instantiated. It should be in the env. Looks like you have it in the driver
UVM_INFO hsio_driver.sv(17) @4100: reporter [reg_adapter] reg2bus" addr = 11da00f0, data = 12345678 kind=0

5

In reply to chr_sue:

Thank you chr_sue,
The log you mentioned was old one, I attached new one at the previous post.
Here again the log


UVM_INFO hsio_reg_adapter.sv(30) @41000000: reporter [reg_adpater] reg2bus: addr = 00000000, data=12341234, kind=0
UVM_INFO hsio_reg_adapter.sv(55) @41000000: reporter [reg_adpater] reg2bus: addr = 00000000, data=0000000, kind=1
UVM_INFO hsio_reg_adapter.sv(30) @41000000: reporter [reg_adpater] reg2bus: addr = 00000004, data=fedcba98, kind=0
UVM_INFO hsio_reg_adapter.sv(55) @41000000: reporter [reg_adpater] reg2bus: addr = 00000004, data=0000000, kind=1

The adapter is


class reg_adapter extends uvm_reg_adapter;
  `uvm_object_utils(reg_adapter)

  function new(string name="reg_adapter");
    super.new(name);
  endfunction

  virtual function uvm_sequence_item reg2bus(const ref ugvm_reg_bus_op rw);
    hsio_seq_item tr;
    tr = hsio_seq_item::type_id::create("tr");
    tr.addr = rw.addr;
    tr.data = rw.data;
    tr.kind = (rw.kind == UVM_READ) ? 1: 0;
    `uvm_info(get_type_name, $sformatf("reg2bus: addr=%h, data=%h, kind=%h",tr.addr, tr.data, tr.kind), UVM_LOW);
    return tr;
  endfunction

  virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
    hsio_seq_item tr;
    if(!$cast(tr, bus_item)) `uvm_fatal(get_type_name(), "Fail to cast seq_item");
    rw.addr = tr.addr;
    rw.data = tr.data;
    rw.kind = (tr.kind) ? UVM_READ : UVM_WRITE;
  endfunction
endclass

register_env is


`include "hsio_reg_adapter.sv"
`include "ral_hsio_cfg_regmodel.sv"

class hsio_reg_env extends uvn_env;
  `uvm_object_utils(hsio_reg_env);
  reg_dapater adapter;
  ral_block_hsio_cfg_regmodel regmodel;

  function new(sting name="hsio_reg_env", uvm_component parent);
    super.new(name, parent);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    adapter = reg_adapter::type_id::create("adapter", this);
    regmodel = ral_block_hsio_cfg_regmodel::type_id::create("regmodel", this);
    regmodel.build();
    regmodel.deault_map.set_base_addr('h0);
    regmodel.reset();
    regmodel.add_hdl_path("TEST_TOP.....");
    regmodel.lock_model();
    regmodel.print();
    uvm_config_db#(ral_block_hsio_cfg_regmodel)::set(null, "uvm_test_top","regmodel",regmodel);
  endfunction
  function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
  endfunction
endclass

top env is


class hsio_env extends uvm_env;
  `uvm_component_utils(hsio_env);
  hsio_agent hsio_agnt;
  hsio_subscriber hsio_sub;
  hsio_reg_env reg_env;

  function new(string name="hsio_env", uvm_component parent);
    super.new(name, parent);
  endfunction
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    hsio_agnt = hsio_agnet::type_id::create("hsio_agnt", this);
    hsio_sub = hsio_subscriber::type_id::create("hsio_sub", this);
    reg_env = hsio_reg_env::type_id::create("reg_env", this);
  endfunction
  function connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    hsio_agnt.monitor.item_collected_port.connect(hsio_sub.analysis_export);
    reg_env.regmodel.default_map.set_sequencer(hsio_agnt.seqr, reg_env.adapter);
  endfunction
endclass

task of test class is


task ral_test::rrun_phase(uvm_phase pahse);
  ral_block_hsio_cfg_regmodel regmodel;
  uvm_status_e status;
  int data;

  phase.raise_objection(this,"Start");
  uvm_config_db#(ral_block_hsio_cfg_regmodel)::get(null,"uvm_test_top","regmodel", regmodel);
  regmodel.CFG_U20H0_BCFG.write(status, 32'h1224_1234);
  regmodel.CFG_U20H0_BCFG.read(status, data);
  regmodel.CFG_U20H0_PCFG0.write(status, 32'hfedcba98);
  regmodel.CFG_U20H0_PCFG0.read(status, data);
  phase.drop_objection(this,"Finish");
  phase.phase_done.set_drain_time(this. 50);
endtask
6

In reply to uvmbee:
Can you share your whole code on EDAPLAYGROUND please?
Or can you share it privately? Then respond on my email
christoph@christoph-suehnel.de

I have to check a few more things.