How the virtual sequencer can help with synchronize control?

Sometimes I found some answers by googling when I was looking for the feasibility of a virtual sequencer.

One of them is that a virtual sequencer can help to stimulus synchronize control.

But actually I didn’t understand how much it would help with stimulus synchronisation control. I think it’s just a handle for something like a container.

So I’d like to know more about how the virtual sequencer can help with synchronize control.

The Virtual sequencer can be used to support the sequencers of multiple agents. For example, if I create a USB, Ethernet, PCIe agent, then each agent has its own sequencer. we can put sequencers in one container as a virtual sequencer but they don’t have any relationships between them. Even if I create some sequences for agents, they don’t have any relationships between them.

So I’m wondering that how the virtual sequencer can help with synchronize control?.

Could you please help me to understand?

In reply to UVM_LOVE:

The role of the virtual sequencer is to run virtual sequences. A virtual sequence is nothing more than a set of sequences, that are targetted to run on different sequencers with some timing control.

For example you may have a virtual sequence for the following scenario.

--------------My first virtual sequence

  • Start a write sequence on the AHB sequencer
  • Wait for 10 clock cycles.
  • Start a read sequence on the AXI sequencer

We may have another virtual sequence defining another scenario as follows

--------------My Second virtual sequence

  • fork
    Start a write sequence on the AHB sequencer
    Start a read sequence on the AXI sequencer
  • join

Each of the above virtual sequence represents a test scenario.
You will be able to start the above virtual sequences on the
virtual sequencer. The timing relationships as expressed in
the above virtual sequences should be obvious (one is a sequential
while the other is a parallel execution.

Hope this helps.

In reply to logie:

It is not a good coding style to deal with clock cycles in the sequences. Any timing should be restricted to drivers and minitors where the pin-level siganls are available. All components above should not deal with pin-level signals including sequences.