How to verify internal states/counters in a DUT?

How to verify whether the DUT internal states or counters are functioning correctly?

For example, a DUT has a counter which increments when there are incoming packets and decrements when packets are being sent out by DUT. How to verify the counter?

I am basically trying to understand how to answer this interview question, not sure if i understood the question right?

A block has inputs of network pkts and buffers/pipelines them through an RTL. RTL has counters which will tell how many packets are sent. How to verify? (Counters Read => count. Write => clear)
How to verify counts? what cases will u test?

In reply to n347:

  • If it is something like a router without any buffer or fixed buffer … then the total of incoming packets should be equal to outgoing packets to make sure no packet is dropped…
  • Datachecks have to be performed to make sure the target address and data sent along are intact
  • You may have to check the order of addresses coming in and going out as well depending on the spec

In reply to n347:

You can verify internal registers like count using SystemVerilog Assertions. If write_enb is asserted, then, the count should be incremented and if rd_enb is asserted, then, the count should be decremented. Please find the below sample code.You can write assertions for internal registers of design in a separate assertion module and bind assertions module to DUT as shown below.


module dut( input clk, wr_enb, rd_enb,
            // and some other input and output signals
			);

	reg [3:0] count; // intenal register
	
	//dut logic which increments count based on wr_enb and rd_enb
endmodule 

module assertion_mod(input clk,wr_enb,rd_enb, [3:0] count);

	property count_incr;
		@(posedge clk) (wr_enb && !rd_enb) |=> count == $past(count) + 1;
	endproperty
	
	property count_decr;
		@(posedge clk) (!wr_enb && rd_enb) |=> count == $past(count) - 1;
	endproperty
	
	property count_stable;
		@(posedge clk) (wr_enb && rd_enb) |=> count == $past(count);
	endproperty

	A1 : assert property (count_incr);
	A2 : assert property (count_decr);
	A3 : assert property (count_stable);
  
endmodule

module top();
	reg wr, rd, clk;
	// declration of other i/o signlas of the DUT
	
	//Instantiation of DUT
	dut d1(clk, wr, rd, .......);
        
        //binding assertions to DUT
	bind dut assertion_mod dut_assertion_mod(.clk(clk), .wr_enb(wr_enb), .rd_enb(rd_enb), .count(count));

endmodule

Hope this helps.

Putta Satish