How to use "wait" for clocking block clock instead of @(cb)

UVM
1

Hi.

I have a clocking block that i want to sync to its clock.

if i use @(cb) i usually get 1 cycle delay if when i get to this line in code it is during the clock posedge of this clocking block.

I would like to use “wait”. how can it be done ? (the clock is not in the list of the clocking block ins\outs)

Thanks !

2

In reply to snognogt:

You should show how your clocking block is defined.
You have 2 options.
using a clocking block or not. You cannot mix the approach.

3

In reply to chr_sue:

Hi

It’s something like that :

interface my_if_t (input logic clk, reset);

    logic  read_done;

    clocking mst_cb @(posedge clk);
        input  reset;
        output read_done;
    endclocking

    clocking prb_cb @(posedge clk);
        input  reset,read_done;
    endclocking

    modport mst (clocking mst_cb);
    modport prb (clocking prb_cb);

endinterface : my_if_t

And i would like to somewhere sync on the posedge clock of this block, but as i said if i make something like @(vif.mst_cb) i miss cycles since waiting for next change in the clocking block clock

thanks :)

4

In reply to snognogt:

Looks correct. Using a clocking block means you are always sync on a certain edge of your clock.Adgain, if you feel the clocking block is causing trouble you should not use it. Aclocking block is always an option.