How to use a virtual interface in uvm?

How to use a virtual interface in uvm?

I found edaplayground.com/x/peeY what I can’t understand about vapb_intf.pclk from task write_drive_apb_packet in apb_master_driver.sv

When I run the simulation, the simulation stuck on @(posedge vapb_intf.pclk); and wait(vapb_intf.pready==1); but I found always #5 apb_intf.pclk=!apb_intf.pclk; in testbench.sv.

I think the connection good. buy why does interface can’t working?

In reply to UVM_LOVE:

In the run_phase of your test you are raising an objection and dropping it at the same time.
This is the reason why your simulation stops at runtime 0.
Additionally your packate variable is initialized to 0.
And again simplify your sequencers body task.
See it is running here: