How to use variable in sequence

define a simple error assertion:
when seeing read request(sending illegal read request), the next read response should issue an error flag, the active cycles of flag depends on request burst length, for example, if request a burst length=3 illegal read, then should receive 3 cycles rvalid & 3 cycles slverr flag. burst_length is variable depends on what uvc sequence picks.
code is like:

sequence s_rd;
   !rvalid [*1: $] ##1 (rvalid&slverr) [*ar_burstlen]
endsequence
property p_rd;
  @(posedge clk iff rst_l) rd_req |-> s_rd );
endproperty
rd_err: assert propery (p_rd) else $error("slave error not detected")

got compile error that:
Error-[NCE] Non-constant expression
The following expression should be a constant.
Expression: ar_burstlen
Source info: !rvalid [*1: $] ##1 (rvalid&slverr) [*ar_burstlen];

How I can pass burst length in to sequence?
Thanks a lot.

In reply to nak_img:

https://verificationacademy.com/forums/systemverilog/assertion-variable-declaration-sva-0#reply-74359

In reply to dave_59:

problem resolved with repeat pkg defined.
Thanks.