Hi,
i have a driver which i want to use uvm_reg_adapter to use this driver in order to inject frontdoor access via ral.
the issue is that my driver sending response back only for read transactions. so its asymmetric.
so i guess i should use provides_responses.
but when doing write tranaction.
i get to this part of code inside task uvm_reg_map::do_bus_write
if (adapter.provides_responses) begin
uvm_sequence_item bus_rsp;
uvm_access_e op;
// TODO: need to test for right trans type, if not put back in q
rw.parent.get_base_response(bus_rsp);
adapter.bus2reg(bus_rsp,rw_access);
and i will never get response …
any other knobs i can use?
how can i handle this asymmetric bus.
thanks
Tal