In reply to dave_59:
Thanks for the feedback Dave.
I changed the code like you suggested and I still see only one of the override takes affect.
Can I override both extended classes together?
What I mean is, when run_phase in component_A is called, it in turn calls display() and display1().
But since, display() is in component_B it must first print "inside display component_B" and then since we call the super.display() it must print "inside Base display component_A"
Similarly, display1() is in component_C it must first print "inside display1 component_C" and then from super.display1() "inside Base display1 component_A"
But in reality only one override takes affect. So, is there a way where I can have both overrides?
I have the expected output after the code.
`include "uvm_macros.svh"
import uvm_pkg::*;
class component_A extends uvm_component;
`uvm_component_utils(component_A)
function new(string name = "component_A", uvm_component parent = null);
super.new(name, parent);
endfunction
virtual function display();
`uvm_info(get_type_name(), $sformatf("inside Base display component_A"), UVM_LOW);
endfunction
virtual function display1();
`uvm_info(get_type_name(), "inside Base display1 component_A", UVM_LOW);
endfunction
task run_phase(uvm_phase phase);
super.run_phase(phase);
`uvm_info("", "Inside base RUN", UVM_LOW)
display();
display1();
endtask
endclass
class component_B extends component_A;
`uvm_component_utils(component_B)
function new(string name = "component_B", uvm_component parent = null);
super.new(name, parent);
endfunction
virtual function display();
`uvm_info(get_type_name(), "inside display component_B", UVM_LOW);
super.display();
endfunction
virtual task run_phase(uvm_phase phase);
`uvm_info("KMK", "Inside ext RUN comp_B", UVM_LOW)
super.run_phase(phase);
endtask
endclass
class component_C extends component_A;
`uvm_component_utils(component_C)
function new(string name = "component_B", uvm_component parent = null);
super.new(name, parent);
endfunction
virtual function display1();
`uvm_info(get_type_name(), "inside display1 component_C", UVM_LOW);
super.display1();
endfunction
task run_phase(uvm_phase phase);
`uvm_info("", "Inside ext RUN comp_C", UVM_LOW)
super.run_phase(phase);
endtask
endclass
class my_test extends uvm_test;
`uvm_component_utils(my_test)
component_A comp_B, comp_C;
function new(string name = "my_test", uvm_component parent = null);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
uvm_factory factory = uvm_factory::get();
super.build_phase(phase);
factory.set_inst_override_by_type(component_A::get_type(), component_B::get_type(), "uvm_test_top.comp_B");
factory.set_inst_override_by_type(component_A::get_type(), component_C::get_type(), "uvm_test_top.comp_C");
comp_C = component_A::type_id::create("comp_C", this);
comp_B = component_A::type_id::create("comp_B", this);
factory.print();
endfunction
function void end_of_elaboration_phase(uvm_phase phase);
super.end_of_elaboration_phase(phase);
uvm_top.print_topology();
endfunction
task run_phase(uvm_phase phase);
super.run_phase(phase);
endtask
endclass
module tb_top;
initial begin
run_test("my_test");
end
endmodule---------------------------------------------------
Actual output
UVM_INFO testbench.sv(64) @ 0: uvm_test_top.comp_C [] Inside ext RUN comp_C
UVM_INFO testbench.sv(21) @ 0: uvm_test_top.comp_C [] Inside base RUN
UVM_INFO testbench.sv(12) @ 0: uvm_test_top.comp_C [component_C] inside Base display component_A
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.comp_C [component_C] inside display1 component_C
UVM_INFO testbench.sv(16) @ 0: uvm_test_top.comp_C [component_C] inside Base display1 component_A
UVM_INFO testbench.sv(42) @ 0: uvm_test_top.comp_B [KMK] Inside ext RUN comp_B
UVM_INFO testbench.sv(21) @ 0: uvm_test_top.comp_B [] Inside base RUN
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.comp_B [component_B] inside display component_B
UVM_INFO testbench.sv(12) @ 0: uvm_test_top.comp_B [component_B] inside Base display component_A
UVM_INFO testbench.sv(16) @ 0: uvm_test_top.comp_B [component_B] inside Base display1 component_A
---------------------------------------------------
What I expected (highlighted what's missing)
UVM_INFO testbench.sv(64) @ 0: uvm_test_top.comp_C [] Inside ext RUN comp_C
UVM_INFO testbench.sv(21) @ 0: uvm_test_top.comp_C [] Inside base RUN
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.comp_C [component_C] inside display component_B
UVM_INFO testbench.sv(12) @ 0: uvm_test_top.comp_C [component_C] inside Base display component_A
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.comp_C [component_C] inside display1 component_C
UVM_INFO testbench.sv(16) @ 0: uvm_test_top.comp_C [component_C] inside Base display1 component_A
UVM_INFO testbench.sv(42) @ 0: uvm_test_top.comp_B [KMK] Inside ext RUN comp_B
UVM_INFO testbench.sv(21) @ 0: uvm_test_top.comp_B [] Inside base RUN
UVM_INFO testbench.sv(36) @ 0: uvm_test_top.comp_B [component_B] inside display component_B
UVM_INFO testbench.sv(12) @ 0: uvm_test_top.comp_B [component_B] inside Base display component_A
UVM_INFO testbench.sv(58) @ 0: uvm_test_top.comp_B [component_B] inside display1 component_C
UVM_INFO testbench.sv(16) @ 0: uvm_test_top.comp_B [component_B] inside Base display1 component_A
