How to use mailbox in uvm environment?

I want to use mailbox for memory sharing purpose at transmitter and receiver sides.
Suppose I have message buffers mapped with a memory with specific address. By using these message buffers how I can configure control and status word of a mailbox.

In reply to MkRishi:

Why you don’t want to use TLM’s to transfer data between components?

In reply to Naven8:

Thank you for writing.
I am not using TLM’s because TLM’s support one directional ports.
I have a scenario for multi master in which every node will share the same address in the memory. All registers are mapped with same memory and configuration same for all nodes

In reply to MkRishi:

I think you may be confusing TLM with uvm_tlm_fifo. The UVM’s TLM ports/exports can certainly be used to implement bi-directional communication. A uvm_tlm_fifo is just an example of a uvm_component with an internal mailbox that exports two TLM ports, a unidirectional put and get port. You can implement your own component with bidirectional exports.

But we would need to know a lot more details about your issue to help with an answer. What kind of control and status of the mailbox does your situation require?