How to use field macros for variables of type "bit" having vector width greater than sizeof(int)? e.g bit[111:0] xyz;

UVM
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Hi Users,

This might be a stupid question, but how can I use field macro when registering with UVM factory in following case.

rand bit[111:0] xyz;

uvm_object_utils_begin(abc_seq_item); uvm_field_???(xyz,UVM_ALL_ON)
`uvm_object_utils_end

What goes at ??? (int or bit or anything else) in the above piece of code? What is the significance of using what we use?

Thanks in advance. Cheers!!!

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In reply to nikhil.n:

The usage of `uvm_field_int does not explicitlly point to the data type ‘int’. It indicates an integral data type, which can be an int, integer, logic, bit etc.

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In reply to chr_sue:

Thank you for your reply.

Does it mean for any width of bit or logic, it won’t have any issues?

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In reply to nikhil.n:

It works for any integral type up to 4096 bits. It’s very inefficient and we suggest not using the field macros. See MacroCostBenefit | Verification Academy

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In reply to dave_59:

Thanks Dave. The video was really helpful.