How to update the Read only register

UVM
1

Hi,

I have a question that how a value is updated to the Read Only register.

Let me elaborate my question

For example : I have a block/IP which has done it’s work and asserted the interrupt, The same can be seen in the INTERRUPT_STATUS_REGISTER which is READ ONLY .

Now, I wanted to know how the value is been updated to that register.

Is there any link lo UVM RAL here ?

Can, someone help me out in this.

Thanks,
durga

2

In reply to durga:

The value of a RO register can only be updated by action internal to the IP block. You need to provide the proper stimulus to your IP block to make that interrupt happen, then it updates the register (if it has been designed correctly).

3

In reply to dave_59:

Thank you dave

I understand what you said

When we do RAL based verification, we have a “uvm_reg_block” from where “My_reg_block” extends, Now My_reg_block contains the Registers that are present in the DUT.

What I wanted to know is, if the register present in “My_reg_block” is RO, How that particular register is updated with a value present in the register(RO) of the DUT since it is RO.

Thanks in advance
durga

4

In reply to durga:

You can also use the Register backdoor access to modify the content of RO registers.

5

In reply to durga:

I think your question is general about how register model’s mirror value synced with DUT. Please read UVM user guide chapter 5.9 for three register model integration approaches and check the diagram read() and write() in the link UVM Tutorial for Candy Lovers – 16. Register Access Methods – ClueLogic which demonstrates the mirror update steps of “explicit prediction” approach.

5.9 Integrating a Register Model
A register model must be integrated with the bus agents that perform and monitor the actual read and write operations.

**There are three structural bus agent integration approaches for keeping the register model’s mirror values in sync with the DUT: implicit prediction, explicit prediction, and passive.
**

Implicit prediction only requires the integration of the register model with one or more bus sequencers. Updates to the mirror are predicted automatically (i.e., implicitly) by the register model after the completion of each read, write, peek, or poke operation. This integration is the simplest and quickest, but it will fail to observe bus operations that did not originate from the register model (e.g., by a third-party bus agent) and thus fail to appropriately update the corresponding mirror values.

Explicit prediction requires the register model be integrated with both the bus sequencers and corresponding bus monitors. In this mode, implicit prediction is turned off and all updates to the mirror are predicted externally (i.e., explicitly) by a uvm_reg_predictor component, one for each bus interface. The predictor receives the bus operations observed by a connected bus monitor, determines the register being accessed by performing a reverse-lookup using the observed address, and then calls the found register’s
predict method explicitly to update the mirror. This integration requires more work, but it will observe all bus operations, whether they originated from the register model or a third-party bus agent, and thus appropriately update the corresponding mirror values.

Passive integration only requires the integration of the register model with the bus monitor as described above. All the monitoring of the register operations is performed externally to (i.e., explicitly) the register model. All bus operations, whether they originated from the register model or a third-party bus agent, are observed and thus appropriately reflected in the corresponding mirror values. Because the register model is
not integrated with a bus sequencer, it cannot be used to read and write register and memories in the DUT, only to track and verify their current value.