How to trigger verilog DUT from C++?

UVM
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How do I start my DUT using CPP only ?

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In reply to Muhamada:

Without knowing how to trigger/start your DUT in Verilog, we cannot give you a complete answer.

There is no concept of time in C++. There are a number of ways to do this, but we need to know more about what kind of stimulus is needed for your DUT to operate. Are there multiple clock? Asynchronous inputs?

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In reply to dave_59:

Hi,

Thanks for you reply.
Lets assume a simple adder, with 2 inputs and 2 outpust with enable signal and a clk and a rest .
and I want to start this DUT with CPP, make a full verification of it but withh CPP only
How such thing will work ?

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In reply to Muhamada:

If you want no Verilog/SystemVerilog code outside the DUT, your best option is using SystemC with your DUT instantiated inside an SC_MODULE. Explaining how to do that is beyond the scope of this forum. Your tools User Manual should explain how mixed language simulation works.