How to traverse each member variable in my_trans

UVM
1

I have some sequence item defined as below.


class my_trans1 extends uvm_sequence_item;
  bit a;
  bit b;
  bit c;
endclass

class my_trans2 extends uvm_sequence_item;
  bit d;
  bit e;
endclass

class my_trans3 extends uvm_sequence_item;
  bit f;
endclass

and I want to create a function to implement that each member variable in each transaction is set to 0 like below psuedo-code shown. Actually it sounds like that the a,b,c in my_trans1 is set to 0 if I called set_zero(my_trans1 tr); and the d,e in my_trans2 will set to 0 if I called set_zero(my_trans2 tr)…


void function set_zero(uvm_sequence_item tr);
  foreach member variable in the tr
    tr.xxx = 0;
  end
endfunction

I am not sure how to achieve it… please help on it if you have any good idea thank you !

2

In reply to zz8318:

SystemVerilog provides no way of iterating over members of a class. The UVM field macros provide a way of unpacking data to each field that you might want to look at. This would not be that efficient, do it might be easier to manually code a set_zero method in each class.

In any case, a uvm_sequence_item base class will not have access to any methods or members in your extension of it.

3

In reply to dave_59:

got it. Thanks for your quick reply