How to track the master number that is writing the register?

UVM
,
1

I have 16 DMA masters running their sequences in parallel and can execute the below line at the same clk.

RFC_SWI.rfc_cmd.write(status, 'hAB);

I think adaptor or some component makes these 16 writes go one after another. But I wanted to know which DMA master value is written 1st, 2nd, etc. Even printing `uvm_info just before the .write is not helping as all the uvm_info msgs from all the 16 dmacs coming at the same time and in one order, but the actual writes or the bus happening in a different order.
In debug, it is becoming very difficult for me to track whose data went 1st, 2nd, etc.

I was thinking is there a way to add one more argument to the write function like below so that I can assign the dma_num to the bus transaction.

RFC_SWI.rfc_cmd.write(status, 'hAB, dma_num);

This is how my adapter reg2bus function looks like:

  
virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
    rffe_rif_seq_item rifmst_rw = rffe_rif_seq_item::type_id::create("rifmst_rw");

    rifmst_rw.m_wr_nrd = (rw.kind == UVM_READ) ? 1'b0: 1'b1;
    rifmst_rw.m_addr   = rw.addr/4;
    rifmst_rw.m_data   = rw.data;
  
    return rifmst_rw;
  endfunction

I tried changing the definition of reg2bus function in the user-defined adaptor but got the compile errors as the reg2bus is defined in the uvm_reg_adaptor like below.

 
virtual class uvm_reg_adapter extends uvm_object;
  pure virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);

Is it a good idea to change this code itself?

Which is the best way to track the dma_num who is giving the write?