I have verilog based testbench top with an initial block with stimulus and has $finish after the test is done. I am trying to integrate an UVM unit environment with this verilog tb. I created module tb_top, which has run_test(), an env, a test, which raises objection, but before dropping objection I would like to know that verilog activity has been done. Similarly, after dropping the objection, I would like send back information to verilog tb to run $finish. I used an interface with an event and placed inside the config_db, however, my simulation hangs as the uvm test waits for the event (blocking). I even used wait(my_event.triggered).
Not sure what is happening? Is there a better way of communicating between verilog testbench and class based testbench?
There is no common answer to your question. It depends on the structure of your TB.
BTW what are you doing with your Verilog TB while having a UVM Environment?
And what is the UVM Environment doing in this strange combination?
You do not need any interface Definition using the Event. Declare them simply in a package.
Did you try for one of the wait the non-blocking event (->>)?
In reply to chr_sue:
Yes. It is a strange combination. I have a verilog based top level tb, in which I would like to use uvm based environment for passive use.
class can b used only in UVM not in verilog,
and uvm have facilty that within a module we can have class