How to switch between RTL and GATE LEVEL paths wihtout updating build block/register model?

UVM
,
1

add_hdl_path(“DUT”, “RTL”) and add_hdl_path(“DUT”, “GATES”); define hdl path for RTL and GATES.

These are defined in build method. How do you switch between RTL or gatelevel simulation without updating reg model?
Is there API that can specify whether RTL or gatelevel netlist model is being used for current simulation run?
Should configdb be used to set the "RTL/“GATES” string of add_hdl_path(…,…)?

2

Wouldn’t tick defines suffice ?

3

In reply to KillSteal:

yes, that is one way. I was looking for some better way.

4

In reply to superUVM:

You would need to describe what metric would make it “better”

If you are switching your DUT from RTL to GATE, you need to go through a complete re-compilation step anyways.

5

In reply to dave_59:

Agreed, except wanted to keep reg model code clean.